Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 175)

Word Addr Bit R/W Name Description
0x4D4
5:0 RO
or
RW
LD coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the
training frame sent from the local device control
channel. Normally, the bits in this register are
read-only; however, when you override training by
setting the
Ovride Coef enable
control bit, these
bits become writeable. The following fields are
defined:
• [5: 4]: Coefficient (+1) update
• 2'b11: Reserved
• 2'b01: Increment
• 2'b10: Decrement
• 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as
[5:4])
• [1:0]: Coefficient (-1) update (same encoding as
[5:4])
For more information, refer to 10G BASE-KR LD
coefficient update register bits (1.154.5:0) in Clause
45.2.1.80.3 of IEEE 802.3ap-2007.
6 RO
or
RW
LD Initialize
Coefficients
When set to 1, requests the link partner coefficients
be set to configure the TX equalizer to its
INITIALIZE state. When set to 0, continues
normal operation. For more information, refer to
10G BASE-KR LD coefficient update register bits
(1.154.12) in Clause 45.2.1.80.3 and Clause
72.6.10.2.3.2 of IEEE 802.3ap-2007.
7 RO
or
RW
LD Preset
Coefficients
When set to 1, requests the link partner coefficients
be set to a state where equalization is turned off.
When set to 0 the link operates normally. For more
information, refer to 10G BASE-KR LD coefficient
update register bit (1.154.13) in Clause 45.2.1.80.3
and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
B-16 10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation Arria 10 10GBASE-KR Registers
Send Feedback