Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 157)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 157
5.1.17.4 PCA9555 Internal Register access
For debug purpose the internal virtual PCA9555 registers can be read by the IPMC and the
Service Processor.
5.1.18 Flash Status and Selection Registers
The flash status register indicates the actual status of the mechanical switches SW1.3 (Signal
BOOT_TSOP), SW3.1 (Signal BOOT_SEL_EN_) and SW3.2 (Signal BOOT_DEFAULT).
The register also provides information about the actual Boot Flash selection (status bit
CURRENT_BOOT_SELECT) and the IPMC selected Boot Flash (status bit
TARGET_BOOT_SELECT).
Table 5-75 Address Control for PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x34
CPU0 Device2 (Slave address 0x21): 0x36
CPU1 Device1 (Slave address 0x20): 0x3C
CPU1 Device1 (Slave address 0x21): 0x3E
Bit Description Default Access
2:0 Internal PCA9555 register address 0 r/w
7:3 Reserved 0 r
Table 5-76 Content of PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x35
CPU0 Device2 (Slave address 0x21): 0x37
CPU1 Device1 (Slave address 0x20): 0x3D
CPU1 Device1 (Slave address 0x21): 0x3F
Bit Description Default Access
7:0 Content of PCA9555 register. 0 r