Sundance SMT6035 v.2.2 - Manual (Page 10)

Version 2.2 Page 10 of 39 SMT6035 User Manual
registers in detail. The standard configuration will connect comport 3 on TIM site
1 to the host.
8.2 The CPLD
The CPLD is used to configure the carrier board. It allows you to select the
direction of signals on the carrier board, to select interrupt sources and to set
the routing of the IIOF lines. The CPLD registers are mapped onto BAR1 of the
PCI bridge chip. The carrier board User Manual includes additional information
about the CPLD.
8.3 State of the IIOF lines
The LINT (local interrupt) line on the global bus side of the PCI bridge chip can
be switched to any of the IIOF lines that go to the DSP.
The initial configuration of the IIOF lines is as follows:
Line Use or direction
IIOF0 Host to DSP
IIOF1 DSP to Host
IIOF2 Used internally by the SMT6035 to signal mailbox interrupts
to the DSP.
Table 1 - Initial state of the IIOF lines when the SMT6035 starts up.
8.4 The PCI bridge chip
The bridge chip represents the link between the host and the carrier board; it
connects the local bus on the carrier board with the PCI bus of the host.
Specific openings are provided to act like windows through which the local bus
can access data on the PCI bus.
The internal PCI bridge registers are mapped onto BAR0, allowing access by
both the local bus (DSP side) and the PCI bus (host side). Contained in the
bridge chip are the 16 x 8-bit mailbox registers (Section 14).
The bridge chip provides a local bus interrupt line (LINT) as well as a PCI bus
interrupt line (IntA). These interrupt lines allow the host side to interrupt the DSP
and vice versa.
More information about the bridge chip can be found at
http://www.quicklogic.com .
User Manual - Version 2.2, 04/01/07; © Sundance Italia S.R.L.