Sundance SMT6035 v.2.2 - Manual (Page 35)

Version 2.2 Page 35 of 39 SMT6035 User Manual
18 PCI bridge chip register access
The Sundance carrier boards use a V3 bridge chip to interface to the PCI bus.
Certain resources, such as I/O address range, memory range and interrupts, are
assigned to the carrier board when the host boots. Information about these
resources is kept in the PCI bridge chip registers.
The PCI bridge chip registers hold, set up and control values; they implement the
mailbox registers too. Although direct access to the mailbox registers (offset
0XC0 – 0xCF) is possible, it is strongly recommended that you use the SMT6035
built-in support (see section 14). This is a consequence of the design of the
interrupt service routine used by the SMT6035.
A special bus cycle on the PCI bus is used to access the PCI registers of the
carrier board. This special bus cycle does not use any BAR mapping, therefore it
is safe to use even if the BAR addresses have not been set up.
You should not need direct access to the PCI registers for most systems. Please
make sure that you know what you are doing before accessing the PCI bridge
chip registers. Writing incorrect values to these registers will almost certainly
crash the host.
For a detailed description of the PCI bridge chip registers, please refer to the
User Manual for the bridge chip here:
http://www.quicklogic.com .
The number at the end of the following function names indicates the number of
bits being read or written.
18.1 PciRead32
Reads 32 bits from the PCI register specified.
Prototype
DWORD IFHw::PciRead32( DWORD dwReg)
18.2 PciWrite32
Writes 32 bits to the PCI register specified.
Prototype
void IFHw::PciWrite32(DWORD dwReg, DWORD dwValue )
18.3 PciWrite16
Writes 16 bits to the PCI register specified.
Prototype
void IFHw::PciWrite16( DWORD dwReg, WORD wValue )
User Manual - Version 2.2, 04/01/07; © Sundance Italia S.R.L.