Sundance SMT148FX - Manual (Page 23)

4.1.21 Local Clock for ADCs etc.
The full functionality of the SMT399-F is also included. This comprises an external
clock input, phase shifter, local OCXO, and 4-way power splitter.
Selection between local OCXO and VGA is made with the position of a 0 Ohm
resistor link. This link (labelled R125) is located on the reverse of the board near the
RS232’s 9-way d-connector. Moving this link will not invalidate any warranty.
Some soldering is necessary to select between the two options.
J1-4 are outputs from a power splitter which is fed from the OCXO. These outputs
are intended for the Sundance range of ADC/DAC modules.
Connector J5 is used for an external clock input which enters the VGA (variable gain
amplifier).
4.1.22 Fan Power
Four two-pin connectors are provided to supply fans using power directly from the
power input connector.
Note that if power is provided via an ATX type supply, then these fan
connectors will be powered at +12V.
4.1.23 Reset Scheme
A power rail monitor observes the state of the 3.3V supply. This device will generate
a reset to the SMT148FX (RESET148) during power-up or if the 3.3V supply drops
below 3V. This signal is an open-collector output and is also driven to the inter-card
ComPort connector, and thus to another SMT148FX.
The POR (power on reset) signal is driven to the RESETOUT pin on the external
ComPort1 connector. The RESETIN pin on the above connector is buffered by an
open-collector device which in turn can also drive the RESET148 signal. An
additional 4 pin header is provided to allow other devices to share the open-
collector RESET148 signal.
The TIM reset pins are connected to the FPGA and will be reset when RESET148 is
active as well as when some firmware conditions trigger a reset to the different TIMs
(see Firmware description for more details about TIM reset).
User Manual SMT148FX Page 23 of 48 Last Edited: 03/08/2009 11:42:00