1 virtex 4 fx, 2 spartan 3, 3 tim sites – Sundance SMT148FX User Manual

Page 8: 4 10/100/1000 ethernet phy, Virtex 4 fx, Spartan 3, Tim sites, 10/100/1000 ethernet phy

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4.1.1 Virtex 4 FX
The primary controlling device on the 148FX is the Xilinx Virtex4 FX60 FPGA. This
device is an FF1152 package which provides 16 MGTs (high speed serial I/O) and
576 normal I/O signals.
This device can be configured via a Xilinx compatible JTAG header.
In normal operation, this device is configured by the CPLD (XC2C512). The
configuration data is stored in flash memory, and is loaded using slave SelectMAP
mode (8-bit parallel).

4.1.2 Spartan 3
The Xilinx Spartan 3 device is similar in nature to that employed on the SMT150Q
and SMT329 carrier boards. It acts as a pre-configured ComPort routing switch.
Different ComPort routing schemes are easy to implement using supplied tools
(requires Xilinx ISE development software).
This device is also configured by the CPLD, and uses slave SelectMAP mode (8-bit
parallel), but is also part of the Xilinx JTAG chain.

4.1.3 TIM Sites
The 148FX provides 4 TIM sites. In addition to the standard specification
requirements, the 148FX also provides the 3.3V supply to the two TIM mounting
holes.
Each TIM site has 4 ComPorts connected directly to the Spartan 3 device. The two
remaining ComPorts are used to create a simple pipe, with each site connecting to
its nearest neighbours.
The TIM site’s interrupt, timer, config, and reset pins are all connected to the Virtex

4 FPGA. The reset signals are asserted during power-up, when pressing the on-board
reset button, or when signalled to via one of the external ComPort connectors.
A global bus connection (16 bit data, 12 bit address) is also made from each site to
the Virtex 4. The global bus connector normally contains one 16-bit SDB interface
(this is unlike the TIM specification which describes the global bus as an
Address/Data structure). These SDBs are the primary method of communication to
the resources shared by the Virtex 4 (eg. USB, Firewire, etc).

4.1.4 10/100/1000 Ethernet Phy
A Marvell Ethernet PHY connects directly to the Virtex 4 FPGA. This interfaces to a
10/100/1000 network via a standard RJ45 socket. This socket has built-in
magnetics.
The PHY is controlled by a MAC within the Virtex 4.

An Ethernet IP core is not supplied in the standard firmware. Please
contact Sundance for further information.

User Manual SMT148FX

Page 8 of 48

Last Edited: 03/08/2009 11:42:00

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