Welltech SPCI2S Intel NetStructure SS7 Boards - Manual (Page 71)

SS7 Programmer’s Manual for SPCI2, SPCI4 and CPM8 Issue 2 Page 71
pll_src
This parameter determines the source of the PLL reference clock, the
permissible values are as follows:
Value PLL clock source
0 No change
1 Clock recovered from one of the line interfaces according to
priority order
5 Local reference oscillator
7 NETREF 1
8 NETREF 2 (CPM8 only)
The PLL clock is used as the reference when acting as CT bus Primary Master.
If the clock is to be recovered from one of the line interfaces then the highest-
priority in sync line interface is used as the reference. Each line interface is
assigned a priority: by default liu_id=0 is the highest priority and liu_id=7 the
lowest. The user may modify the priority order by sending the
MVD_MSG_CLOCK_PRI message. If none of the interfaces are available for
recovery then the phase locked loop will run in holdover mode, outputting a
clock with the same frequency as the last valid signal. When a valid signal
returns it will wait for a short period to verify that it is stable and then
automatically switch to use it as the clock reference.
If using one of the NETREF signals as the reference source then another board
in the system should be providing this reference by driving a clock source onto
the appropriate CT bus NETREF lines. If the NETREF signal is lost the board
will continue with the PLL in holdover mode until another
MVD_MSG_CNFCLOCK message is sent in to switch to a new mode.
NOTE: If the NETREF signal recovers it is still necessary to re-set the clock
configuration and move out of holdover mode by sending
MVD_MSG_CNFCLOCK and re-selecting the appropriate mode.