Grass Valley 8920ADC v.2.0.1A - Manual (Page 36)

36 8920ADC Instruction Manual
Functional Description
Digital Reference Input
The digital reference is applied via the loop-through input to the AES
receiver and phase-locked loop. This provides clock and data to the Control
and Routing FPGA and the A/D converters.
Routing and Control FPGA
The signals from the A/D converters are applied to the Routing and
Control FPGA. The incoming signal processing and level is determined by
the setting of one of 16 possible mode commands from a four-bit rotary
encoder switch and four signals from the level toggle switches. After pro-
cessing, the signals are embedded into an AES stream and applied to the
Output Drivers.
The Routing and Control section also drives the front panel LEDs and inter-
faces to the Controller section.
Controller
The Controller interfaces with the Routing and Control FPGA, the
EEPROM and the 8900 Frame Bus. The Controller also provides the FPGA
code that is downloaded to the FPGA during boot-up.
The Controller section handles local control and monitoring, as well as
remote control and monitoring via the frame bus (when an 8900NET
module is installed in the frame). Module settings are stored in the
EEPROM for power up recall.
Power Supply
Power is fed from ±12 V rails of the frame’s switching power supply. Each
stage of the module receives it’s own, separate, highly regulated and fil-
tered power source. Two-stage regulation is used in the analog section of
the ADC to reduce switching noise.