EPoX Computer KP6-FX2 - Manual (Page 28)

• CPU-To-PCI Write Post:
Enabled: Writes from the CPU to the PCI bus are buffered, to compensate
for the speed differences between the CPU and the PCI bus.
Disabled: The writes are not buffered and the CPU must wait until the write
is complete before starting another write cycle.
• CPU-To-PCI IDE Posting:
Enabled: To post write cycles from the CPU to the PCI IDE interface. IDE
accesses are posted in the CPU to PCI buffers, for cycle optimiza-
tion.
Disabled: Doesn’t post write cycles from the CPU to the PCI buffers.
• System BIOS Cacheable:
Enabled: Allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
Disabled: System BIOS non-cacheable
• Video BIOS Cacheable: Allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance. The default value
is Enabled.
Enabled: Enables the Video BIOS Cacheable to speed up the VGA Perfor-
mance.
Disabled: Will not use the Video BIOS Cacheable function.
• 8/16 Bit I/O Recovery Time: The default value is 1.
8 Bit I/O Recovery Time: This field defines the recovery time from
1 to 8 for 8-bit I/O.
16 Bit I/O Recovery Time: To define the recovery time from 1 to 4
for 16-bit I/O.
• Memory Hole at 15M-16M: The default value is Disabled.
Disabled: Normal Setting.
Enabled : This field enables the main memory (15~16MB) remap to ISA
BUS.
• DRAM Fast Landoff: Shorten the leadoff cycles to optimize performance.
• Passive Release: The default value is enabled
• Delayed Transaction: The defaul value is disabled.
KP6-FX 2 3-9