ELAN Home Systems EM78P458 - Manual (Page 16)

EM78P458/459
OTP ROM
1 = The Vref of the ADC is connected to P53/VREF.
• Bit 6 (CE): Comparator enable bit
0 = Comparator is off (default value);
1 = Comparator is on.
• Bit 5 ( COE ): Set P57 as the output of the comparator
0 = the comparator acts as an OP if CE=1.
1 = act as a comparator if CE=1.
• Bit4:Bit2 (IMS2:IMS0):
Input Mode Select. ADC configuration definition bit. The following Table describes how to define the
characteristic of each pin of R6.
Table 3 Description of AD Configuration Control Bits
IMS2:IMS0 P60 P61 P62 P63 P64 P65 P66 P67
000 A D D D D D D D
001 A A D D D D D D
010 A A A D D D D D
011 A A A A D D D D
100 A A A A A D D D
101 A A A A A A D D
110 A A A A A A A D
111 A A A A A A A A
• Bit 1: Bit 0 (CKR1: CKR0): The prescaler of oscillator clock rate of ADC
00 = 1: 4 (default value);
01 = 1: 16;
10 = 1: 64;
11 = The oscillator clock source of ADC is from WDT ring oscillator frequency.
( frequency=256/18ms≒14.2Khz)
6. IOCB0 (Pull-down Control Register)
7 6 5 4 3 2 1 0
/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0
• Bit 0 (/PD0) Control bit is used to enable the pull-down of the P60 pin.
0: Enable internal pull-down;
1: Disable internal pull-down.
• Bit 1 (/PD1) Control bit is used to enable the pull-down of the P61 pin.
• Bit 2 (/PD2) Control bit is used to enable the pull-down of the P62 pin.
• Bit 3 (/PD3) Control bit is used to enable the pull-down of the P63 pin.
This specification is subject to change without prior notice. 07.01.2003 (V1.3) 16