Otp rom 4.15 instruction set – ELAN Home Systems EM78P458 User Manual
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EM78P458/459
OTP ROM
4.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. Normally, all instructions are executed within one single instruction cycle (one instruction
consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A",
"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2",
⋅⋅⋅⋅). In this case, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O registers can be regarded as general registers. That is, the same instruction can operate
on I/O registers.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general-purpose registers) is to be utilized by the instruction. The symbol
"b" represents a bit field designator that selects the value for the bit located in the register "R" that is
affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value.
Table 16 The list of the instruction set of EM78P458/459
INSTRUCTION BINARY HEX MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000
0000
NOP
No Operation
None
0 0000 0000 0001
0001
DAA
Decimal Adjust A
C
0 0000 0000 0010
0002
CONTW
A
→ CONT
None
0 0000 0000 0011
0003
SLEP
0
→ WDT, Stop oscillator
T,P
0 0000 0000 0100
0004
WDTC
0
→ WDT
T,P
0 0000 0000 rrrr
000r
IOW R
A
→ IOCR
None <Note1>
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack]
→ PC
None
0 0000 0001 0011
0013
RETI
[Top of Stack]
→ PC, Enable Interrupt
None
0 0000 0001 0100
0014
CONTR
CONT
→ A
None
0 0000 0001 rrrr
001r
IOR R
IOCR
→ A
None <Note1>
0 0000 01rr rrrr
00rr
MOV R,A
A
→ R
None
0 0000 1000 0000
0080
CLRA
0
→ A
Z
0 0000 11rr rrrr
00rr
CLR R
0
→ R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A
→ A
Z,C,DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A
→ R
Z,C,DC
0 0001 10rr rrrr
01rr
DECA R
R-1
→ A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1
→ R
Z
0 0010 00rr rrrr
02rr
OR A,R
A
∨ VR → A
Z
0 0010 01rr rrrr
02rr
OR R,A
A
∨ VR → R
Z
0 0010 10rr rrrr
02rr
AND A,R
A & R
→ A
Z
0 0010 11rr rrrr
02rr
AND R,A
A & R
→ R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A
⊕ R → A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A
⊕ R → R
Z
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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