Otp rom, Fig. 14 the output timing of the pwm – ELAN Home Systems EM78P458 User Manual

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EM78P458/459

OTP ROM

Data Bus

Data Bus

PRD1

Com parator

Com parator

TM R1H + TM R1L

S

R

Q

M UX

Duty Cycle

M atch

Period
M atch

PW M 1

T1P0 T1P1 T1EN

IOC51

PRD2

Com parator

Com parator

S

R

Q

M UX

Duty Cycle

M atch

Period
M atch

PW M 2

T2P0 T2P1 T2EN

IOC51

To PW M 1IF

To PW M 2IF

reset

reset

latch

latch

1:2
1:8
1:32

Fosc

1:64

1:2
1:8
1:32

Fosc

1:64

TM R2H + TM R2L

DT2H
+
DT2L

DT1H

+

DT1L

DL2H + DL2L

DL1H + DL1L

Fig. 13 The Functional Block Diagram of the Dual PWMs

Period

Duty Cycle

DT1 = TMR1

PRD1 = TMR1

Fig. 14 The Output Timing of the PWM

2. Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L )

TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM

module as baud rate clock generators. TMRX can be read, written, and cleared at any reset

conditions. If employed, they can be turned down for power saving by setting T1EN bit

[PWMCON<4>] or T2EN bit [PWMCON<5>] to 0.

This specification is subject to change without prior notice. 07.01.2003 (V1.3)

38

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