Document Outline

• IMPORTANT NOTICE
• Read This First
  • About This Manual
  • Notational Conventions
  • Related Documentation From Texas Instruments
  • Trademarks
• Contents
• Figures
• Tables
• Chapter 1: Overview
  • 1.1 Video Port
  • 1.2 Video Port FIFO
    • 1.2.1 DMA Interface
    • 1.2.2 Video Capture FIFO Configurations
    • 1.2.3 Video Display FIFO Configurations
  • 1.3 Video Port Registers
  • 1.4 Video Port Pin Mapping
    • 1.4.1 VDIN Bus Usage for Capture Modes
    • 1.4.2 VDOUT Data Bus Usage for Display Modes
• Chapter 2: Video Port
  • 2.1 Reset Operation
    • 2.1.1 Power-On Reset
    • 2.1.2 Peripheral Bus Reset
    • 2.1.3 Software Port Reset
    • 2.1.4 Capture Channel Reset
    • 2.1.5 Display Channel Reset
  • 2.2 Interrupt Operation
  • 2.3 DMA Operation
    • 2.3.1 Capture DMA Event Generation
    • 2.3.2 Display DMA Event Generation
    • 2.3.3 DMA Size and Threshold Restrictions
    • 2.3.4 DMA Interface Operation
  • 2.4 Clocks
  • 2.5 Video Port Functionality Subsets
    • 2.5.1 Data Bus Width
    • 2.5.2 FIFO Size
  • 2.6 Video Port Throughput and Latency
    • 2.6.1 Video Capture Throughput
    • 2.6.2 Video Display Throughput
  • 2.7 Video Port Control Registers
    • 2.7.1 Video Port Control Register (VPCTL)
    • 2.7.2 Video Port Status Register (VPSTAT)
    • 2.7.3 Video Port Interrupt Enable Register (VPIE)
    • 2.7.4 Video Port Interrupt Status Register (VPIS)
• Chapter 3: Video Capture Port
  • 3.1 Video Capture Mode Selection
  • 3.2 BT.656 Video Capture Mode
    • 3.2.1 BT.656 Capture Channels
    • 3.2.2 BT.656 Timing Reference Codes
    • 3.2.3 BT.656 Image Window and Capture
    • 3.2.4 BT.656 Data Sampling
    • 3.2.5 BT.656 FIFO Packing
  • 3.3 Y/C Video Capture Mode
    • 3.3.1 Y/C Capture Channels
    • 3.3.2 Y/C Timing Reference Codes
    • 3.3.3 Y/C Image Window and Capture
    • 3.3.4 Y/C FIFO Packing
  • 3.4 BT.656 and Y/C Mode Field and Frame Operation
    • 3.4.1 Capture Determination and Notification
    • 3.4.2 Vertical Synchronization
    • 3.4.3 Horizontal Synchronization
    • 3.4.4 Field Identification
    • 3.4.5 Short and Long Field Detect
  • 3.5 Video Input Filtering
    • 3.5.1 Input Filter Modes
    • 3.5.2 Chrominance Resampling Operation
    • 3.5.3 Scaling Operation
    • 3.5.4 Edge Pixel Replication
  • 3.6 Ancillary Data Capture
    • 3.6.1 Horizontal Ancillary (HANC) Data Capture
    • 3.6.2 Vertical Ancillary (VANC) Data Capture
  • 3.7 Raw Data Capture Mode
    • 3.7.1 Raw Data Capture Notification
    • 3.7.2 Raw Data FIFO Packing
  • 3.8 TSI Capture Mode
    • 3.8.1 TSI Capture Features
    • 3.8.2 TSI Data Capture
    • 3.8.3 TSI Capture Error Detection
    • 3.8.4 Synchronizing the System Clock
    • 3.8.5 TSI Data Capture Notification
    • 3.8.6 Writing to the FIFO
    • 3.8.7 Reading from the FIFO
  • 3.9 Capture Line Boundary Conditions
  • 3.10 Capturing Video in BT.656 or Y/C Mode
    • 3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode
  • 3.11 Capturing Video in Raw Data Mode
    • 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode
  • 3.12 Capturing Data in TSI Capture Mode
    • 3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode
  • 3.13 Video Capture Registers
    • 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT)
    • 3.13.2 Video Capture Channel A Control Register (VCACTL)
    • 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTR\ T1)
    • 3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP\ 1)
    • 3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTR\ T2)
    • 3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP\ 2)
    • 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VC\ BVINT)
    • 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)\
    • 3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT\ )
    • 3.13.10 Video Capture Channel B Control Register (VCBCTL)
    • 3.13.11 TSI Capture Control Register (TSICTL)
    • 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL)
    • 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM)
    • 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL)
    • 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM)
    • 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL)
    • 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM)
    • 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)
    • 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)
    • 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS)
  • 3.14 Video Capture FIFO Registers
• Chapter 4: Video Display Port
  • 4.1 Video Display Mode Selection
    • 4.1.1 Image Timing
    • 4.1.2 Video Display Counters
    • 4.1.3 Sync Signal Generation
    • 4.1.4 External Sync Operation
    • 4.1.5 Port Sync Operation
  • 4.2 BT.656 Video Display Mode
    • 4.2.1 Display Timing Reference Codes
    • 4.2.2 Blanking Codes
    • 4.2.3 BT.656 Image Display
    • 4.2.4 BT.656 FIFO Unpacking
  • 4.3 Y/C Video Display Mode
    • 4.3.1 Y/C Display Timin Reference Codes
    • 4.3.2 Y/C Blanking Codes
    • 4.3.3 Y/C Image Display
    • 4.3.4 Y/C FIFO Unpacking
  • 4.4 Video Output Filtering
    • 4.4.1 Output Filter Modes
    • 4.4.2 Chrominance Resampling Operation
    • 4.4.3 Scaling Operation
    • 4.4.4 Edge Pixel Replication
  • 4.5 Ancillary Data Display
    • 4.5.1 Horizontal Ancillary (HANC) Data Display
    • 4.5.2 Vertical Ancillary (VANC) Data Display
  • 4.6 Raw Data Display Mode
    • 4.6.1 Raw Mode RGB Output Support
    • 4.6.2 Raw Data FIFO Unpacking
  • 4.7 Video Display Field and Frame Operation
    • 4.7.1 Display Determination and Notification
    • 4.7.2 Video Display Event Generation
  • 4.8 Display Line Boundary Conditions
  • 4.9 Display Timing Examples
    • 4.9.1 Interlaced BT.656 Timing Example
    • 4.9.2 Interlaced Raw Display Example
    • 4.9.3 Y/C Progressive Display Example
  • 4.10 Displaying Video in BT.656 or Y/C Mode
  • 4.11 Displaying Video in Raw Data Mode
    • 4.11.1 Handling Underrun Condition of the Display FIFO
  • 4.12 Video Display Registers
    • 4.12.1 Video Display Status Register (VDSTAT)
    • 4.12.2 Video Display Control Register (VDCTL)
    • 4.12.3 Video Display Frame Size Register (VDFRMSZ)
    • 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)
    • 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1\ )
    • 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)\
    • 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2\ )
    • 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)\
    • 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)
    • 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)
    • 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2)
    • 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2)
    • 4.12.13 Video Display Field 1 Timing Register (VDFLDT1)
    • 4.12.14 Video Display Field 2 Timing Register (VDFLDT2)
    • 4.12.15 Video Display Threshold Register (VDTHRLD)
    • 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)
    • 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (\ VDVSYNS1)
    • 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VD\ VSYNE1)
    • 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (\ VDVSYNS2)
    • 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VD\ VSYNE2)
    • 4.12.21 Video Display Counter Reload Register (VDRELOAD)
    • 4.12.22 Video Display Display Event Register (VDDISPEVT)
    • 4.12.23 Video Display Clipping Register (VDCLIP)
    • 4.12.24 Video Display Default Display Value Register (VDDEFVAL)
    • 4.12.25 Video Display Vertical Interrupt Register (VDVINT)
    • 4.12.26 Video Display Field Bit Register (VDFBIT)
    • 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)\
    • 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)\
  • 4.13 Video Display Registers Recommended Values
  • 4.14 Video Display FIFO Registers
• Chapter 5: General Purpose I/O Operation
  • 5.1 GPIO Registers
    • 5.1.1 Video Port Peripheral Identification Register (VPPID)
    • 5.1.2 Video Port Peripheral Control Register (PCR)
    • 5.1.3 Video Port Pin Function Register (PFUNC)
    • 5.1.4 Video Port Pin Direction Register (PDIR)
    • 5.1.5 Video Port Pin Data Input Register (PDIN)
    • 5.1.6 Video Port Pin Data Output Register (PDOUT)
    • 5.1.7 Video Port Pin Data Set Register (PDSET)
    • 5.1.8 Video Port Pin Data Clear Register (PDCLR)
    • 5.1.9 Video Port Pin Interrupt Enable Register (PIEN)
    • 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)
    • 5.1.11 Video Port Pin Interrupt Status Register (PISTAT)
    • 5.1.12 Video Port Pin Interrupt Clear Register (PICLR)
• Chapter 6: VCXO Interpolated Control Port
  • 6.1 Overview
  • 6.2 Interface
  • 6.3 Operational Details
  • 6.4 Enabling VIC Port
  • 6.5 VIC Port Registers
    • 6.5.1 VIC Control Register (VICCTL)
    • 6.5.2 VIC Input Register (VICIN)
    • 6.5.3 VIC Clock Divider Register (VICDIV)
• Appendix A: Video Port Configuration Examples
  • A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format
  • A.2 Example 2: Noncontinuous Frame Display for 525/60 Format
• Index