Texas Instruments TMS320C64x DSP User Manual
Page 235
Video Display Registers
Video Display Port
4-90
SPRU629
4.12.27
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
The video display field 1 vertical blanking bit register (VDVBIT1) controls the
V bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1
is shown in Figure 4–66 and described in Table 4–32.
The VBITSET1 and VBITCLR1 bits control the V bit value in the EAV and SAV
timing control codes. The V bit is set to 1 (indicating the start of field 1 digital
vertical blanking) in the EAV code at the beginning of the line whenever the
frame line counter (FLCOUNT) is equal to VBITSET1. It remains a 1 for all
EAV/SAV codes until the EAV at the beginning of the line on when
FLCOUNT = VBITCLR1 where it changes to 0 (indicating the start of the
field 1 digital active display). The V bit operation is completely independent of
the VBLNK control signal.
The VBITSET1 and VBITCLR1 bits should be programmed so that FLCOUNT
becomes set to 1 during field 1 vertical blanking. The hardware only starts
generating field 1 EDMA events when FLCOUNT = 1.
Figure 4–66. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
31
28
27
16
Reserved
VBITCLR1
R-0
R/W-0
15
12
11
0
Reserved
VBITSET1
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset