Texas Instruments TMS320C64x DSP - Manual (Page 62)

Video Port Control Registers
2-29 Video Port SPRU629
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)
Bit Description Value symval field
3 SERRA Channel A synchronization error interrupt detected bit.
BT.656 or Y/C capture mode – Synchronization parity error on
channel A. An SERRA typically requires resetting the channel
(RSTCH) or the port (VPRST).
Raw data mode or TSI capture mode – Not used.
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
2 CCMPA Capture complete on channel A interrupt detected bit. (Data is not
in memory until the DMA transfer is complete.)
BT.656 or Y/C capture mode – CCMPA is set after capturing an
entire field or frame (when F1C, F2C, or FRMC in VCASTAT are
set) depending on the CON, FRAME, CF1, and CF2 control bits in
VCACTL.
Raw data mode – If RDFE bit is set, CCMPA is set when F1C,
F2C, or FRMC in VCASTAT is set (when the data counter = the
combined VCYSTOP/VCXSTOP value) depending on the CON,
FRAME, CF1, and CF2 control bits in VCACTL. If RDFE bit is not
set, CCMPA is set when FRMC in VCASTAT is set (when the data
counter = the combined VCYSTOP/VCXSTOP value).
TSI capture mode – CCMPA is set when FRMC in VCASTAT is set
(when the data counter = the combined VCYSTOP/VCXSTOP
value).
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
1 COVRA Capture overrun on channel A interrupt detected bit. COVRA is set
when data in the FIFO was overwritten before being read out (by
the DMA).
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
0 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
† For CSL implementation, use the notation VP_VPIS_field_symval