FUJITSU MHV2160BT - Manual (Page 187)

5.3 Host Commands
C141-E239 5-111
*10 Word 64: Advance PIO transfer mode support status
Bits 15-8: Reserved
Bits 7-0: Advance PIO transfer mode
Bit 1: '1' = Mode 4 supported
Bit 0: '1' = Mode 3 supported
*11 WORD 75: X ' 001F ' (32)
*12 WORD 76
Bits 15-11: Reserved
Bit 10: '1' = Supports the PHY event counter.
Bit 9: '1' = Supports the Power Management initiation request from
the host system.
Bit 8: '1' = Supports the Native command queueing.
Bits 7-4: Reserved
Bit 3: Reserved for SATA
Bit 2: '1' = Supports the Gen-2 signaling rete.
Bit 1: '1' = Supports the Gen-1 signaling rete.
Bit 0: Reserved
*13 WORD 78
Bits 15-7: Reserved
Bit 6: '1' = Supports the software settings preservation.
Bit 5: Reserved
Bit 4: '1'= Supports the in-order data delivery.
Bit 3: '1'= Supports the Power Management initiation from the device to
the host system.
Bit 2: '1' = Supports the DMA Setup FIS Auto-Activate optimization.
Bit 1: '1' = Supports the non-zero buffer offset in the DMA Setup FIS.
Bit 0: Reserved