Document Outline

• Revision History
• Table of Contents
• List of Figures
• List of Tables
• Preface
  • Table 0-1 List of MC9S12C and MC9S12GC Family members
  • Table 0-2 MC9S12C-Family Package Option Summary
  • Figure 0-1 Order Part number Coding
  • Table 0-3 MC9S12C-Family Part Number Coding
  • Table 0-4 MC9S12GC-Family Part Number Coding
  • Table 0-5 Document References
    • Terminology
• Section 1 Introduction
  • 1.1 Overview
  • 1.2 Features
  • 1.3 Modes of Operation
  • 1.4 Block Diagram
    • Figure 1-1 MC9S12C-Family Block Diagram
  • 1.5 Device Memory Map
    • Table 1-1 Device Register Map Overview
    • Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map
    • Figure 1-3 MC9S12C96 User Configurable Memory Map
    • Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map
    • Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map
    • Figure 1-6 MC9S12GC16 User Configurable Memory Map
  • 1.6 Detailed Register Map
    • $0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
    • $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
    • $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)
    • $0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)
    • $0018 - $0018 Miscellaneous Peripherals (Device User Guide)
    • $0019 - $0019 VREG3V3 (Voltage Regulator)
    • $001A - $001B Miscellaneous Peripherals (Device User Guide)
    • $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,
    • Device User Guide)
    • $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
    • $001F - $001F INT map 2 of 2 (HCS12 Interrupt)
    • $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)
    • $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)
    • $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
    • $0034 - $003F CRG (Clock and Reset Generator)
    • $0040 - $006F TIM (Timer 16 Bit 8 Channels)
    • $0070 - $007F Reserved
    • $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)
    • $00A0 - $00C7 Reserved
    • $00C8 - $00CF SCI (Asynchronous Serial Interface)
    • $00D0 - $00D7 Reserved
    • $00D8 - $00DF SPI (Serial Peripheral Interface)
    • $00E0 - $00FF PWM (Pulse Width Modulator)
    • $0100 - $010F Flash Control Register
    • $0110 - $013F Reserved
    • $0140 - $017F CAN (Motorola Scalable CAN - MSCAN)
    • Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
    • $0180 - $023F Reserved
    • $0240 - $027F PIM (Port Interface Module)
    • $0280 - $03FF Reserved space
  • 1.7 Part ID Assignments
    • Table 1-3 Assigned Part ID Numbers
    • Table 1-4 Memory size registers
• Section 2 Signal Description
  • 2.1 Device Pinout
    • Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family
    • Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family
    • Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family
  • 2.2 Signal Properties Summary
    • Table 2-1 Signal Properties
  • 2.3 Detailed Signal Descriptions
    • Figure 2-4 PLL Loop Filter Connections
    • Figure 2-5 Colpitts Oscillator Connections (PE7=1)
    • Figure 2-6 Pierce Oscillator Connections (PE7=0)
    • Figure 2-7 External Clock Connections (PE7=0)
  • 2.4 Power Supply Pins
    • Table 2-2 MC9S12C-Family Power and Ground Connection Summary
• Section 3 System Clock Description
  • Figure 3-1 Clock Connections
• Section 4 Modes of Operation
  • 4.1 Overview
  • 4.2 Chip Configuration Summary
    • Table 4-1 Mode Selection
    • Table 4-2 Clock Selection Based on PE7
  • 4.3 Security
  • 4.4 Low Power Modes
• Section 5 Resets and Interrupts
  • 5.1 Overview
  • 5.2 Vectors
    • Table 5-1 Interrupt Vector Locations
  • 5.3 Resets
    • Table 5-2 Reset Summary
• Section 6 HCS12 Core Block Description
  • 6.1 Device-specific information
    • Table 6-1 Device Specific Flash PAGE Mapping
• Section 7 Voltage Regulator (VREG) Block Description
  • 7.1 Device-specific information
• Section 8 Recommended Printed Circuit Board Layout
  • Table 8-1 Recommended External Component Values
  • Figure 8-1 Recommended PCB Layout (48 LQFP)
  • Figure 8-2 Recommended PCB Layout (52 LQFP)
  • Figure 8-3 Recommended PCB Layout (80 QFP)
  • Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
  • Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
  • Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
• Section 9 Clock Reset Generator (CRG) Block Description
  • 9.1 Device-specific information
• Section 10 Oscillator (OSC) Block Description
• Section 11 Timer (TIM) Block Description
• Section 12 Analog to Digital Converter (ATD) Block Description
  • 12.1 Device-specific information
• Section 13 Serial Communications Interface (SCI) Block Description
• Section 14 Serial Peripheral Interface (SPI) Block Description
• Section 15 Flash Block Description
• Section 16 RAM Block Description
• Section 17 Pulse Width Modulator (PWM) Block Description
• Section 18 MSCAN Block Description
• Section 19 Port Integration Module (PIM) Block Description
• Appendix A Electrical Characteristics
  • A.1 General
    • Table A-1 Absolute Maximum Ratings
    • Table A-2 ESD and Latch-up Test Conditions
    • Table A-3 ESD and Latch-Up Protection Characteristics
    • Table A-4 Operating Conditions
    • Table A-5 Thermal Package Characteristics
    • Table A-6 5V I/O Characteristics
    • Table A-7 3.3V I/O Characteristics
    • Table A-8 Supply Current Characteristics for MC9S12C32
    • Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128
• Appendix B Electrical Specifications
  • B.1 Voltage Regulator Operating Conditions
    • Table B-1 Voltage Regulator Electrical Parameters
  • B.2 Chip Power-up and LVI/LVR graphical explanation
    • Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
  • B.3 Output Loads
    • Table B-2 Voltage Regulator - Capacitive Loads
  • B.4 ATD Characteristics
    • Table B-3 ATD Operating Characteristics
    • Table B-4 ATD Operating Characteristics
    • Table B-5 ATD Electrical Characteristics
    • Table B-6 ATD Conversion Performance
    • Table B-7 ATD Conversion Performance
    • Figure B-2 ATD Accuracy Definitions
  • B.5 NVM, Flash and EEPROM
    • Table B-8 NVM Timing Characteristics
    • Table B-9 NVM Reliability Characteristics
  • B.6 Reset, Oscillator and PLL
    • Table B-10 Startup Characteristics
    • Table B-11 Oscillator Characteristics
    • Figure B-3 Basic PLL functional diagram
    • Figure B-4 Jitter Definitions
    • Figure B-5 Maximum bus clock jitter approximation
    • Table B-12 PLL Characteristics
  • B.7 MSCAN
    • Table B-13 MSCAN Wake-up Pulse Characteristics
  • B.8 SPI
• Appendix C Electrical Specifications
  • Table C-1 Measurement Conditions
  • C.1 Master Mode
    • Figure C-1 SPI Master Timing (CPHA=0)
    • Figure C-2 SPI Master Timing (CPHA=1)
    • Table C-2 SPI Master Mode Timing Characteristics
  • C.2 Slave Mode
    • Figure C-3 SPI Slave Timing (CPHA=0)
    • Figure C-4 SPI Slave Timing (CPHA=1)
    • Table C-3 SPI Slave Mode Timing Characteristics
  • C.3 External Bus Timing
    • Figure C-5 General External Bus Timing
    • Table C-4 Expanded Bus Timing Characteristics (5V Range)
    • Table C-5 Expanded Bus Timing Characteristics (3.3V Range)
• Appendix D Package Information
  • D.1 General
  • D.2 80-pin QFP package
    • Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
  • D.3 52-pin LQFP package
    • Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)
  • D.4 48-pin LQFP package
    • Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)
• Appendix E Emulation Information
  • E.1 General
    • Figure 19-1 Pin Assignments in 112-pin LQFP
  • E.2 112-pin LQFP package
    • Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (ca...
• Device User Guide End Sheet