Intel IQ80333 - Manual (Page 37)

Customer Reference Board Manual 37
Intel® IQ80333 I/O Processor
Hardware Reference Section
3.8 Board Reset Scheme
Figure 10 depicts the reset scheme for the 80333. Table 14 list the reset schemes for the 80333.
Table 14. Reset Requirements/Schemes
Description
Primary PCI reset, resets all devices on the board. It occurs during the power-up.
The SRST signal from the JTAG connector is a bi-directional signal that can force a reset similar to the
power-up reset on the board.
Figure 10. RESET Sources
DDR II SDRAM
Intel® 80333 I/O
Processor
PCI-X Con A
PCI-X Con B
JTAG
Con
Debounce
CPLD
A_RST#
B_RST#
RST#
LAN_PWR_GOOD
PWRGD
TRST
#
SRST
#
Power
Delay
RESETIN
#
Reset
Button
82545EM
TRST
#
M_RST#
PWRDELAY
PCI-E Con
Pwrgood
Isolation
Voltage
Monitor