Ami post code – Intel IM-Q35 Series User Manual
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4-3
System Reso urces
AMI POST Code
Ch eckpoint
Descript ion
Before D0
If boot block debugger is en abled, CPU cache-as-RAM f unctionalit y is
enabled at this point. St ack will be enabled fr om this point.
D0
Early Boot S trap Processor (BSP) initialization like micr oco de update,
f requency and other CP U critic al initialization. Early chipset initialization is
d one.
D1
Early super I/O initializat ion is do ne including RTC and keyb oard
controller. Se rial port is enabled at t his point if needed for debugging. NMI
is disabled. P erform keyboard controller B AT test. S ave power-on CPUID
value in scratch CMOS. Go to flat mode with 4GB limit and G A20
enabled.
D2
Verif y the boot b lock chec ksum. S ystem will h ang here if chec ksum is
b ad.
D3
Disable CACHE bef ore memory d etection. Execute full memory sizing
module. If memory sizing module not executed, start memory refr esh and
d o memory sizing in Boot block code. Do additional chipset initialization.
Re- enable CACH E. V erif y t hat flat mo de is enabled.
D4
Test base 512KB memory. Adjust policies and cache f irst 8MB. Set stack.
D5
Bootblock code is copied from ROM t o lower system memory and control
is given to it. B IOS n ow execut es out of RAM. Copies compr essed boot
block c od e to memory in rig ht segments. Copies BIOS from ROM to RAM
f or fast er access. Performs main BIOS checksum and up dates recovery
status accord ingly.
D6
Both key seq uence and OEM specific meth od is ch ecked to det ermine if
BIOS recovery is forced. If BIOS recovery is necessar y, control f lows t o
checkpoint E 0. See Bootblock Recovery Code Checkpoints section of
d ocu ment for more infor mation.
D7
Rest or e CPUID value b ack into register. The Bootblock-Runtime
interf ac e module is moved to sys tem memory and control is given to it.
Determine wheth er to exec ute serial f lash.
D8
The Runtime module is uncompressed in to memor y. CPUID inf ormation
is store d in memory.
D9
Store the Uncompressed pointer for futu re use in PMM. Copyin g Main
BIOS int o memo ry. Le ave s all RAM below 1MB Read-W rite including
E000 and F000 shadow areas but closing SMRAM.
DA
Rest or e CPUID value back into register. Give contr ol to BIOS P OST
(ExecutePOSTKernel). See POST Cod e Checkpoin ts section of
d ocu ment for more infor mation.
DC
System is waking from ACPI S3 state
E1-E8
EC-EE
OE M memor y detection/co nfiguration error. This range is reserved for
chipset vendors & system man ufactu rers. Th e error associated with this
value may be diff erent f rom one p latform to th e next .
Bootblock Initialization Code Checkpoints
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