Intel IM-Q35 Series User Manual

Page 66

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4-5

System Reso urces

I nitialize t he flop py controlle r in the su per I/O. Som e int errupt vectors
are initialized. DMA controller is in itialized. 825 9 interrupt controller is
initia lize d. L 1 cache is en abled.

Set up f loppy c ontroller a nd data. Att empt to r ead f rom flopp y.

Ena ble AT API hard ware. Att empt to read from ARMD and ATA PI

Disable A TAPI h ardware. Ju mp back t o checkpoint E9.

Read error occurred on med ia. Ju mp b ack to checkpoint EB .

defin ed recovery file n ame in root directory.

Start reading FAT tab le a nd ana lyze FAT t o f ind th e clusters occupied

Start re adin g th e recovery file clust er b y cluste r.

Check the validit y of t he r ecover y f ile conf iguration t o the current
conf igu ration of th e flash part.

Make f lash writ e enable d th rough chipset and OEM sp ecific met hod.
Detect prop er flash pa rt. V er if y th at th e fou nd f lash p art size equals th e

file size does n ot eq ual th e found flash part size.

T he flash has been u pd ated successf ully. Make flash writ e d isabled.
Disable AT API h ard ware. R est ore CPUID value back int o regist er.

o F0 00 ROM at F000: FFF0h.

Checkpoint

D escription

03

Disab le NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS,
POST, Runtime dat a area. Also initialize BIOS modules on POST entry
and GPNV area. Init ialized C MOS as mention ed in the Kernel Variable
"wCMOSFlags."

04

Check CMOS diagnostic byte to determine if battery p ower is OK and
CMOS checksu m is OK. Verify CMOS checksum man ually b y reading
storage area. If the CMOS ch ecksum is bad, update CMOS with power- on
def ault values an d clea r passwords. Initialize status register A.

Initializes data variables t hat are based on CMOS s et up questions.
Initializes both the 8259 compatible PICs in the system

05

Initializes t he interrupt controlling hardw are (generally PIC) and interrupt
vect or table.

06

D o R/W test to CH-2 c ount reg. Initialize CH-0 as syst em timer.Install th e
POSTINT1Ch handler . Enable IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to "POSTINT1ChH andlerBlock."

07

Fixes CPU POST interfac e calling point er.

08

Initializes the CPU. The BAT test is being done on KBC. Program the
keyb oard controller command byte is being done aft er Auto d etection of
KB/MS using AMI KB-5.

C0

Early CPU Init Start -- Dis able Cache

– Init Local APIC

C1

Set up boot strap p roc essor Information

C2

Set up boot strap p roc essor for POST

C5

En umerate and set up application processors

C6

R e-enable cache for boot strap process or

C7

Early CPU Init Exit

0A

Initializes the 8042 compatible Key Boa rd Cont roller.

0B

D etects the pres ence of PS/2 mouse.

0C

D etects the pres ence of Keyboard in KBC port.

0E

Testing and initializat ion of different Input D evices . Also, updat e the
Kern el Variables.

Traps the INT09h vec tor, so that the POST INT09h handler g ets control
for IRQ1. Uncompress all availab le language, BIOS logo, an d Silen t logo
modules.

13

Early POST initialization of chipset registers.

20

R elocate System Man agement Interrupt vector for all CPU in the system.

24

Uncompress and initialize any platf orm specific BIOS modules. GPNV is
in itialized at this checkpoint.

2A

Initializes different devices thr ough DIM.
See DIM Code Checkp oin ts section of document for mor e inf ormation.

2C

Initializes differ ent devices. D etects and init ializes the video adap ter
in stalled in the syst em t hat have optional ROMs.

2E

Initializes all the ou tput devices.

31

Allocate memory f or ADM module and uncompress it. Give control t o
AD M module for initialization. Initialize language and font modu les for
AD M. Activate ADM module.

33

Initializes the silent boot module. Set the window f or displaying text
in format ion.

37

Displaying sign-on message, CPU information, setup key message, and
any OEM specific information.

38

Initializes different devices t hrough DIM. See DIM Code Checkpoints
sect ion of document for more information. USB c ontrollers are initialized
at t his point.

POST Code Checkpoints

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