4 pci target interface, Table 3.1 pci address spaces, Pci target interface – SMSC LAN9420 User Manual
Page 26: Pci configuration space registers, Control and status registers (csr), Csr endianness, Datasheet 3.2.4 pci target interface
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
26
SMSC LAN9420/LAN9420i
DATASHEET
3.2.4
PCI Target Interface
The PCI target interface implements the address spaces listed in
The PCI Configuration space is used to identify PCI Devices, configure memory ranges, and manage
interrupts. The Host initializes and configures the PCI Device during a plug-and-play process.
The PCI Target Interface supports 32-bit slave accesses only. Non 32-bit PCI target reads to
LAN9420/LAN9420i will result in a full 32-bit read. Non 32-bit PCI target writes to LAN9420/LAN9420i
will be silently discarded.
3.2.4.1
PCI Configuration Space Registers
PCI Configuration Space Registers include the standard PCI header registers and PCIB extensions to
implement power management control/status registers. See
Section 4.6, "PCI Configuration Space
CSR (CONFIG CSR)," on page 149
for further details. These registers exist in the configuration space.
3.2.4.2
Control and Status Registers (CSR)
The PCI Target Interface allows PCI bus masters to directly access the LAN9420/LAN9420i Control
and Status registers via memory or I/O operations. Each set of operations has an associated address
range that defines it as follows:
The non-prefetchable (NP) address range is mapped in BAR3. No data prefetch is performed when
serving PCI transactions targeting this address range.
The I/O address range is mapped in BAR4.
3.2.4.2.1
CSR ENDIANNESS
The Non-Prefetchable address range contains a double mapping of the CSR. These mappings allow
the registers to be accessed in little endian or big endian order.
Figure 3.3, "CSR Double Endian
illustrates the mapping. BA is the base address, as specified by BAR3.
Table 3.1 PCI Address Spaces
SPACE
SIZE
RESOURCE
Configuration
256 bytes
PCI standard and PCIB-specific registers
BAR0...BAR2
RESERVED
BAR3
1 KB
Control and Status Registers (Non-prefetchable area)
BAR4
256B
Control and Status Registers (I/O area)
BAR5
RESERVED
Expansion ROM
-
RESERVED