SMSC LAN9420 - Manual (Page 76)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 76 SMSC LAN9420/LAN9420i
DATASHEET
3.7.4.1.2 EXITING THE G3 STATE
When the system leaves the G3 state, the device will behave as follows. State transitions are illustrated
in
Figure 3.28 on page 75 .
„ G3 to D3
COLD
(T6): This transition occurs when VAUXDET is connected to the PCI 3.3Vaux power
supply and all power is off (PCInRST=X, PM_STATE=X, VAUXDET=0, PWRGOOD=0) and then
3.3Vaux is applied (PCInRST=0, PM_STATE=X, VAUXDET=0 to 1, PWRGOOD=0).
LAN9420/LAN9420i detects the application of auxiliary power and asserts its internal power-on
reset (POR). POR resets the
PME Enable (PME_EN) bit of the PCI Power Management Control
and Status Register (PCI_PMCSR) and sets the Power Management State (PM_STATE) field of
the PCI Power Management Control and Status Register (PCI_PMCSR) to the “D3” state. The
internal PHY is held in the general-power down state and the device is powered by the PCI 3.3Vaux
supply. The device will remain in the D3
COLD
state until PCI power is applied.
3.7.4.2 D0
UNINTIALIZED
State (D0
U
)
In this state all internal clocks are enabled, but the device has not been initialized by the PCI Host.
The device cannot receive or transmit Ethernet data. Depending on the reason for the transition into
D0
U
, the PHY may have been reset and may be in the General Power-Down state. These conditions
are noted in the discussions that follow.
In D0
U
the device will respond to all PCI accesses. While in this state, the Power Management State
(PM_STATE) field of the PCI Power Management Control and Status Register (PCI_PMCSR) will
indicate a setting of 00b (D0 state).
3.7.4.2.1 EXITING THE D0
U
STATE
The device will exit the D0
U
state under the following conditions. State transitions are illustrated in
Figure 3.28 on page 75 .
„ D0
U
to D3
HOT
(T1): This transition occurs when the Host system selects the “D3” state in the Power
Management State (PM_STATE) field of the PCI Power Management Control and Status Register
(PCI_PMCSR) . PCI main and auxiliary power (if used) remain on (PCInRST=1, PM_STATE=00b
to 11b, VAUXDET=X, PWRGOOD=1).
„ D0
U
to D0
A
(T2): This transition occurs when the device is in the D0
U
uninitialized state and is then
configured by the PCI Host. (PCInRST=1, PM_STATE=00b, VAUXDET=X, PWRGOOD=1).
„ D0
U
to D3
COLD
(T10): This transition occurs when all power supplies are operational and the Power
Management State (PM_STATE) field of the PCI Power Management Control and Status Register
(PCI_PMCSR) is set to “D0”, but the device has not yet been initialized, and then PCI power is
turned off and 3.3Vaux is still operational (PCInRST=1, PM_STATE=00b, VAUXDET=1,
PWRGOOD=1 to 0). The internal PHY is reset and is placed in the General Power-Down mode on
this transition. Note that if VAUXDET=0, the device is being powered from the PCI +3.3V supply
and will turn off (G3) when PCI power is removed.
„ D0
U
to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
3.7.4.3 D0
ACTIVE
State (D0
A
)
In this state all internal clocks are operational and the device is able to receive and transmit Ethernet
data. This is the normal operational state of the device.
In D0
A
the device will respond to all PCI accesses. While in this state, the Power Management State
(PM_STATE) field of the PCI Power Management Control and Status Register (PCI_PMCSR) will
indicate a setting of 00b (D0 state).
3.7.4.3.1 POWER MANAGEMENT EVENTS IN D0
A
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link
status change) wake events and is capable of asserting a PCI interrupt (nINT) or nPME as a result of