National Instruments Signal Processing Engineering Educational Device NI SPEEDY-33 - Manual (Page 27)

Appendix A Specifications
NI SPEEDY-33 User Manual A-2 ni.com
DSP
DSP .........................................................TMS320VC33
• High-performance floating-point digital signal processor (DSP)
– 150 million floating-point operations per second (MFLOPS)
– 75 million instructions per second (MIPS)
• 34 K
× 32 bit (1.1-Mbit) on-chip words of dual-access static
random-access memory (SRAM) configured in 2 × 16 K
plus 2
× 1 K blocks to improve internal performance
• 32-bit high-performance CPU
• 16/32-bit integer and 32/40-bit floating-point operations
• Boot-program loader
• 32-Bit instruction word, 24-Bit Addresses
• Fabricated using the 0.18-
μm (l
eff
-effective gate length) TImeline
technology by Texas Instruments (TI)
• On-chip memory-mapped peripherals
– Direct Memory Access (DMA)
– Coprocessor for concurrent I/O and CPU operation
• Parallel arithmetic/logic unit (ALU) and multiplier execution in a
single cycle
• Supports standalone operation
Bus Interface
USB ........................................................Full speed 1.1
Power Requirements
Input voltage
External power supply
powered operation ...........................9 VDC at 500 mA at power port
with appropriate safety and EMC
Certification marks, which are
acceptable in the country in which
the product is to be installed
USB powered operation ..................USB bus power
Device maximum current .......................0.233 A