Renesas M3A-HS85 - Manual (Page 20)

Functional Overview
2.3 Memory
Rev.1.04 2008.7.10 2-4
REJ10J1564-0104
2
2.3 Memory
2.3.1 SH7285 On-Chip Memory
The SH7285 includes a 768-Kbytes flash memory and 32-Kbytes RAM.
2.3.2 SRAM
Two Mbytes of SRAM can be mounted on the M3A-HS85 (Not mounted). In the M3A-HS85 specification, 3.3V
power is supplied to SRAM so that SH7285 should be used in 3.3V when SRAM is mounted (CPU power supply
switch jumper (JP1) should be set to
“2-3”). SRAM is controlled by the bus state controller built into SH7285. The
address spaces of SRAM can be switched to CS0 space, CS2 space, and CS6 space by the pin function controller
setting of SH7285.
Table 2.3.1 lists the SRAM specifications. Figure 2.3.1 shows the block diagram for the connection between
SH7285 and SRAM.
Table 2.3.1 SRAM Specifications
Part Number Bus size Capacity Package
R1LV1616RSA-7S 16 bit 2 Mbytes (16-bit x 1M word x 1 pc.) 48-pin TSOP (20 x 12mm)
SH7285
PB11/CS0/CS2/CS6
PA14/RD
PA8/RDWR
16M-bit SRAM
(1M Word ×16bit)
20
16
BYTE
CS1
OE
WE
UB
LB
Reset
A19 - A0 PB8/A20 - PC1/A1
DQ15 - DQ0 PD15/D15 - PD0/D0
PA12/WRH
PA13/WRL
CS2
3.3V
R1LV1616RSA-7
Figure 2.3.1 Block Diagram for Connection Between SH7285 and SRAM