Texas Instruments TMS320 DSP - Manual (Page 63)

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6.3 Requirements for the Use of the DMA Resource
6.4 Logical Channel
Requirements for the Use of the DMA Resource
through the logical DMA channels it acquires through the IDMA2 protocol.
A detailed description of these APIs can be found in the TMS320 DSP Algorithm Standard API Reference
(SPRU360).
Below is a list of requirements for DMA usage in eXpressDSP-compliant algorithms. These requirements
will help to clarify the intent of the stated rules and guidelines in this chapter.
1. All physical DMA resources must be owned and managed by the framework.
2. Algorithms must access the DMA resource through a handle representing a logical DMA channel
abstraction. These handles are granted to the algorithm by the framework using a standard IDMA
interface.
3. A mechanism must be provided so that algorithms can ensure completion of data transfer(s).
4. The DMA scheme must work within a preemptive environment.
5. It must be possible for an algorithm to request multiframe data transfers (two-dimensional data
transfers).
6. The framework must be able to obtain the worst-case DMA resource requirements at algorithm
initialization time.
7. The DMA scheme must be flexible enough to fit within static and dynamic systems, and systems with a
mix of static and dynamic features.
8. All DMA operations must complete prior to return to caller. The algorithm must synchronize all DMA
operations before return to the caller from a framework-callable operation.
9. It must be possible for several algorithms to share a physical DMA channel.
DSP algorithms, depending on the type of algorithm and the execution flow of the algorithm, might
schedule the use of the DMA resource in different ways. For example:
•
An algorithm might need to do a DMA transfer based on results after decoding an encoded bit stream.
The results from these calculations determine the source, destination, and configuration of a DMA data
transfer. All this information must be passed to the DMA device to start the data transfer. This type of
data transfer is data dependent, and its configuration must therefore be determined on-the-fly.
•
An algorithm might schedule a fixed number of DMA data transfers into its program flow and the
configuration of these transfers might be the same. It is only necessary to provide the source and
destination information to execute these data transfers, since the configuration is fixed. This type of
data transfer is not data-dependent; its configuration can be predetermined.
•
Some algorithms might have a mixture of the above scenarios. These algorithms have some
predetermined data transfers and some data dependent data transfers.
When using the IDMA interfaces, a DMA handle is granted to the algorithm by the framework during
initialization. This handle can be further utilized by the ACPY2 APIs used by IDMA2 or custom protocols
used by IDMA3, to configure, request and synchronize the data transfers
The term "logical channel" is associated with each DMA handle that the framework provides to the
algorithm and represents an abstraction for a dedicated" private DMA channel. The algorithm owns the
logical channel it receives. The algorithm uses the channel handles to configure the channel DMA transfer
settings, submit asychronous DMA transfer requests, and query and synchronize with the completion
status of scheduled transfers. The logical channel retains its state and applies the most recent
configuration settings when scheduling a transfer. The channel configuration determines, for example, the
size of the elements and the number of frames in multiframe transfers. A data transfer description is
complete when the source and destination information and the frame length are added to the logical
channel's configuration.
The logical channel concept can be used intelligently by the algorithm designer to optimize the algorithm's
performance. For example, algorithms with data transfers using the same configuration may request one
logical channel for all these transfers. This logical channel does not need to be configured for each
transfer. Furthermore, the algorithm may request another logical channel for the data-dependent transfers.
This logical channel must be configured for each transfer.
SPRU352G – June 2005 – Revised February 2007 Use of the DMA Resource 63
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