Texas Instruments TMS320 DSP - Manual (Page 72)

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DMA/CPU idle
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CPU context switch
CPU/DMA active
Algorithm A
active
Algorithm B
active
CPU context
(timeline)
DMA context
(timeline)
1 2 3 4 5
6.15.3 Preemptive System
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DMA/CPU idle
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CPU context switch
CPU/DMA activ
Algorithm A
active
Algorithm B
active active
Algorithm A
CPU context
(timeline)
DMA context
(timeline)
1 2 3 4 5 6 7
Inter-Algorithm Synchronization
Events
1. Algorithm A requests a data transfer by calling ACPY2_start() . The framework executes this request
immediately since the DMA channel is free.
2. Algorithm A calls ACPY2_wait() to wait for the data transfer to complete. The framework checks to see
that the data are still being transferred.
3. The data transfer is complete and the framework returns control to Algorithm A so it can process the
transferred data.
4. Algorithm B requests a data transfer by calling ACPY2_start() .The framework executes this request
immediately since the DMA channel is free.
5. Algorithm B calls ACPY2_complete() to check if the data transfer has completed. The framework
checks to see that the data has been transferred. Algorithm B can process the transferred data.
Notice that algorithm A must wait for the transfer to complete because the parallel CPU processing takes
less time than the data transfer, whereas algorithm B's data transfer has completed at the time of
synchronization.
In summary, we can see from Section 6.15.2 that sharing a physical DMA channel between several
algorithms is trivial as long as the algorithms don't preempt each other.
Sharing a physical DMA channel among two algorithms in a preemptive system requires some procedure
to manage the shared resource. The system must have a policy for handling the situation where one
algorithm preempts another algorithm while the shared physical DMA channel is currently being used.
Let's assume that the framework preempts algorithm A in order to run algorithm B.
•
Scenario 1: The system policy is to abort the current DMA transfer to free-up the DMA device to the
higher priority algorithm. See
Section 6.15.4 .
The system's policy is to abort the current DMA transfer when context switching to a higher priority
72 Use of the DMA Resource SPRU352G – June 2005 – Revised February 2007
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