Texas Instruments TMS320DM643X DMP - Manual (Page 3)

Preface ....................................................................................................................................... 6
1 Introduction ........................................................................................................................ 7
1.1 Purpose of the Peripheral .............................................................................................. 7
1.2 Features .................................................................................................................. 7
1.3 Functional Block Diagram
..............................................................................................
8
1.4 Industry Standard(s) Compliance Statement
........................................................................
8
2 Peripheral Architecture ...................................................................................................... 10
2.1 Clock Generation and Control
........................................................................................
10
2.2 Signal Descriptions .................................................................................................... 12
2.3 Pin Multiplexing ........................................................................................................ 12
2.4 Protocol Description
...................................................................................................
12
2.5 Endianness Considerations .......................................................................................... 13
2.6 Operation
................................................................................................................
14
2.7 Reset Considerations
..................................................................................................
18
2.8 Initialization
.............................................................................................................
18
2.9 Interrupt Support
.......................................................................................................
18
2.10 DMA Event Support
...................................................................................................
20
2.11 Power Management ................................................................................................... 20
2.12 Emulation Considerations ............................................................................................. 20
2.13 Exception Processing ................................................................................................. 21
3 Registers .......................................................................................................................... 21
3.1 Receiver Buffer Register (RBR)
......................................................................................
22
3.2 Transmitter Holding Register (THR) ................................................................................. 23
3.3 Interrupt Enable Register (IER) ...................................................................................... 24
3.4 Interrupt Identification Register (IIR) ................................................................................ 25
3.5 FIFO Control Register (FCR)
.........................................................................................
26
3.6 Line Control Register (LCR)
..........................................................................................
28
3.7 Modem Control Register (MCR) ..................................................................................... 30
3.8 Line Status Register (LSR) ........................................................................................... 31
3.9 Divisor Latches (DLL and DLH) ...................................................................................... 33
3.10 Peripheral Identification Registers (PID1 and PID2)
..............................................................
35
3.11 Power and Emulation Management Register (PWREMU_MGMT)
..............................................
36
Appendix A Revision History ...................................................................................................... 37
3 SPRU997C – December 2009 Table of Contents
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