Texas Instruments TMS320DM643X DMP - Manual (Page 33)

www.ti.com Registers
Table 17. Line Status Register (LSR) Field Descriptions (continued)
Bit Field Value Description
0 DR Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit
is set (ERBI = 1 in IER), an interrupt request is generated.
In non-FIFO mode:
0 Data is not ready, or the DR bit was cleared because the character was read from the receiver buffer
register (RBR).
1 Data is ready. A complete incoming character has been received and transferred into the receiver buffer
register (RBR).
In FIFO mode:
0 Data is not ready, or the DR bit was cleared because all of the characters in the receiver FIFO have
been read.
1 Data is ready. There is at least one unread character in the receiver FIFO. If the FIFO is empty, the DR
bit is set as soon as a complete incoming character has been received and transferred into the FIFO.
The DR bit remains set until the FIFO is empty again.
3.9 Divisor Latches (DLL and DLH)
Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the
baud clock in the baud generator. The latches are in DLH and DLL. DLH holds the most-significant bits of
the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded
during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the
divisor latches results in two wait states being inserted during the write access while the baud generator is
loaded with the new value.
Access considerations:
• RBR, THR, and DLL share one address. When DLAB = 1 in LCR, all accesses at the shared address
are accesses to DLL. When DLAB = 0, reading from the shared address gives the content of RBR, and
writing to the shared address modifies THR.
• IER and DLH share one address. When DLAB = 1 in LCR, accesses to the shared address read or
modify to DLH. When DLAB = 0, all accesses at the shared address read or modify IER.
DLL and DLH also have dedicated addresses. If you use the dedicated addresses, you can keep the
DLAB bit cleared, so that RBR, THR, and IER are always selected at the shared addresses.
The divisor LSB latch (DLL) is shown in Figure 17 and described in Table 18 . The divisor MSB latch (DLH)
is shown in Figure 18 and described in Table 19 .
33 SPRU997C – December 2009 Universal Asynchronous Receiver/Transmitter (UART)
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