Xilinx ML310 - Manual (Page 15)

ML310 User Guide www.xilinx.com 15
UG068 (v1.01) August 25, 2004 1-800-255-7778
Foundation ISE R
IP. ISE even includes technology called IP Builder, which allows you to capture your own
IP and reuse it in other designs.
ISE’s Architecture Wizards allow easy access to device features like the Digital Clock
Manager and Multi-Gigabit I/O technology.
ISE also includes a tool called PACE (Pinout Area Constraint Editor) which includes a
front-end pin assignment editor, a design hierarchy browser, and an area constraint editor.
By using PACE, designers are able to observe and describe information regarding the
connectivity and resource requirements of a design, resource layout of a target FPGA, and
the mapping of the design onto the FPGA via location/area.
This rich mixture of design entry capabilities provides the easiest to use design
environment available today for your logic design.
Synthesis
Synthesis is one of the most essential steps in your design methodology. It takes your
conceptual Hardware Description Language (HDL) design definition and generates the
logical or physical representation for the targeted silicon device.
A state of the art synthesis engine is required to produce highly optimized results with a
fast compile and turnaround time. To meet this requirement, the synthesis engine needs to
be tightly integrated with the physical implementation tool and have the ability to
proactively meet the design timing requirements by driving the placement in the physical
device. In addition, cross probing between the physical design report and the HDL design
code will further enhance the turnaround time.
Xilinx ISE provides the seamless integration with the leading synthesis engines from
Mentor Graphics, Synopsys, and Synplicity. You can use the synthesis engine of our choice.
In addition, ISE includes Xilinx proprietary synthesis technology, XST. You have options to
use multiple synthesis engines to obtain the best-optimized result of your programmable
logic design.
Implementation and Configuration
Programmable logic design implementation assigns the logic created during design entry
and synthesis into specific physical resources of the target device.
The term “place and route” has historically been used to describe the implementation
process for FPGA devices and “fitting” has been used for CPLDs. Implementation is
followed by device configuration, where a bitstream is generated from the physical place
and route information and downloaded into the target programmable logic device.
To ensure designers get their product to market quickly, Xilinx ISE software provides
several key technologies required for design implementation:
•
Ultra-fast runtimes enable multiple “turns” per day
•
ProActive™ Timing Closure drives high-performance results
•
Timing-driven place and route combined with “push-button” ease
•
Incremental Design
•
Macro Builder