Rainbow Electronics MAX16066 - Manual (Page 28)

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16065/MAX16066
28 _____________________________________________________________________________________
Critical Faults
During normal operation, a fault condition can be con-
figured to shut down all the EN_OUT_s and store fault
information in the flash memory by setting the appropri-
ate critical fault enable bits. During power-up and pow-
er-down, all sequenced MON_ inputs are considered
critical. Faults during power-up and power-down always
cause the EN_OUT_s to turn off and can store fault infor-
mation in the flash memory, depending on the contents
of r6Dh[1:0]. Set the appropriate critical fault enable bits
in registers r6Eh to r72h (see Table 18) for a fault condi-
tion to trigger a critical fault.
Logged fault information is stored in flash registers r200h
to r20Fh (see Table 19). After fault information is logged,
the flash is locked and must be unlocked to enable a
new fault log to be stored. Write a ‘0’ to r8Ch[1] to unlock
the FAULT flash. Fault information can be configured to
store ADC conversion results and/or fault flags in regis-
ters. Select the critical fault configuration in r6Dh[1:0].
Set r6Dh[1:0] to ‘11’ to turn off the fault logger. All stored
ADC results are 8 bits wide.
Power-Up/Power-Down Faults
All EN_OUT_s deassert when an overvoltage or under-
voltage fault is detected during power-up/power-down
and the MAX16065/MAX16066 return to the power-
off condition. Fault information can be stored to flash
depending on r6D[1:0], see Table 18. GPIO3 and
GPIO8 can be configured as power-up fault outputs
(ANY_FAULT).
Autoretry/Latch Mode
The MAX16065/MAX16066 can be configured for one
of two fault management methods: autoretry or latch-
on fault. Set r74h[4:3] to ‘00’ to select the latch-on-fault
mode. In this configuration, EN_OUT_s deassert after
a critical fault event. The device does not reinitiate the
power-up sequence until EN is toggled or the Software
Enable bit is toggled. See the Enable section for more
information on setting the software enable bit.
Table 16. Deglitch Configuration
Table 17. Fault Flags
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE DESCRIPTION
73h 273h [6:5]
Overcurrent Comparator Deglitch Time:
00 = No deglitch
01 = 4ms
10 = 15ms
11 = 60ms
74h 274h [6:5]
Voltage Comparator Deglitch Configuration:
00 = 2 cycles
01 = 4 cycles
10 = 8 cycles
11 = 16 cycles
REGISTER
ADDRESS
BIT RANGE DESCRIPTION
1Bh
[0] MON1
[1] MON2
[2] MON3
[3] MON4
[4] MON5
[5] MON6
[6] MON7
[7] MON8