Rainbow Electronics MAX16066 - Manual (Page 35)

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16065/MAX16066
______________________________________________________________________________________ 35
Watchdog Timer
The watchdog timer operates together with or indepen-
dently of the MAX16065/MAX16066. When operating in
dependent mode, the watchdog is not activated until the
sequencing is complete and RESET is deasserted. When
operating in independent mode, the watchdog timer is
independent of the sequencing operation and activates
immediately after V
CC exceeds the UVLO threshold and
the boot phase is complete. Set r73h[4] to ‘0’ to config-
ure the watchdog in dependent mode. Set r73h[4] to ‘1’
to configure the watchdog in independent mode. See
Table 24 for more information on configuring the watch-
dog timer in dependent or independent mode.
Dependent Watchdog Timer Operation
Use the watchdog timer to monitor FP activity in two
modes. Flexible timeout architecture provides an adjust-
able watchdog startup delay of up to 300s, allowing com-
plicated systems to complete lengthy boot-up routines.
An adjustable watchdog timeout allows the supervisor to
provide quick alerts when processor activity fails. After
each reset event (V
CC drops below UVLO then returns
above UVLO, software reboot, manual reset (MR), EN
input going low then high, or watchdog reset) and once
sequencing is complete, the watchdog startup delay
provides an extended time for the system to power up
and fully initialize all FP and system components before
assuming responsibility for routine watchdog updates.
Set r76h[6:4] to a value other than ‘000’ to enable the
watchdog startup delay. Set r76h[6:4] to ‘000’ to disable
the watchdog startup delay.
Table 22. EN_OUT_ GPIO_ State Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE DESCRIPTION
1Fh —
[0] EN_OUT9 input state
[1] EN_OUT10 input state
[2] EN_OUT11 input state
[3] EN_OUT12 input state
34h 234h
[0] 1 = Assert EN_OUT9
[1] 1 = Assert EN_OUT10
[2] 1 = Assert EN_OUT11
[3] 1 = Assert EN_OUT12
Figure 6. RESET and EN_OUT_ During Power-Up, EN_OUT_ in
Open-Drain Active-Low Configuration
MAX16065 fig06
20ms/div
V
CC
2V/div
EN_OUT_
2V/div
0V
RESET
2V/div
0V
0V
MAX16065 fig07
10ms/div
V CC
2V/div
EN_OUT_
2V/div
0V
RESET
2V/div
0V
0V
HIGH-Z
ASSERTED
LOW
UVLO
Figure 7. RESET and EN_OUT_ During Power-Up, EN_OUT_ in
Push-Pull Active-High Configuration