Rainbow Electronics ATtiny43U - Manual (Page 107)

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8048B–AVR–03/09
14.4 Alternative USI Usage
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
14.4.1 Half-Duplex Asynchronous Data Transfer
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
14.4.2 4-Bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
14.4.3 12-Bit Timer/Counter
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
14.4.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
14.4.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
14.5 Register Descriptions
14.5.1 USICR – USI Control Register
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. See the USISIF bit description in
“Analog Comparator” on page 112 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when
the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.
See the USIOIF bit description in
“Analog Comparator” on page 112 for further details.
• Bit 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and Shift Register can therefore be clocked exter-
Bit 7 6 5 4 3 2 1 0
0x0D (0x2D) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0