Rainbow Electronics ATtiny43U - Manual (Page 135)

135
8048B–AVR–03/09
18.5 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
18.6 Reading the Fuse and Lock Bits from Software
It is possible for firmware to read device fuse and lock bits. In addition, firmware can also read
data from the device signature imprint table (see
page 141 ).
Note: Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-
grammed, will be read as one.
18.6.1 Reading Lock Bits from Firmware
Lock bit values are returned in the destination register after an LPM instruction has been issued
within three CPU cycles after RFLB and SPMEN bits have been set in SPMCSR. The RFLB and
SPMEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction
is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.
When RFLB and SPMEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
If successful, the contents of the destination register are as follows.
See section “Program And Data Memory Lock Bits” on page 139 for more information.
18.6.2 Reading Fuse Bits from Firmware
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
If successful, the contents of the destination register are as follows.
Refer to Table 19-5 on page 141 for a detailed description and mapping of the Fuse Low Byte.
Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0