Rainbow Electronics ADC08351 - Manual (Page 12)

Applications Information
(All schematic
pin numbers refer to the TSSOP.) (Continued)
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in video (high frequency) systems,
however, avoid crossing analog and digital lines altogether.
Furthermore, it is important to keep any clock lines isolated
from ALL other lines, including other digital lines. Even the
generally accepted 90 degree crossing should be avoided as
even a little coupling can cause problems at high frequen-
cies.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 3 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
4.0 DYNAMIC PERFORMANCE
The ADC08351 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital
circuitry should be done with adequate buffers, as with a
clock tree. See Figure 4.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. Even
lines with 90˚ crossings have capacitive coupling, so try to
avoid even these 90˚ crossings of the clock line.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or
signal edges, like the 74F and the 74AC(T) families. In
general, slower logic families, such as 74LS and 74HC(T)
will produce less high frequency noise than do high speed
logic families, such as the 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is narrow compared with the rest of
the ground plane. This narrowing beneath the converter
provides a fairly high impedance to the high frequency com-
ponents of the digital switching currents, directing them
away from the analog pins. The relatively lower frequency
analog ground currents do not create a significant variation
across the impedance of this relatively narrow ground con-
nection.
5.0 TYPICAL APPLICATION CIRCUITS
Figure 5 shows a simple interface for a low impedance
source located close to the converter. As discussed in Sec-
tion 1.0, the series capacitor is optional. Notice the isolation
of the ADC clock signal from the clock signals going else-
where in the system. The reference input of this circuit is
shown connected to the 3V supply.
Video ADCs tend to have input current transients that can
upset a driving source, causing distortion of the driving sig-
nal. The resistor at the ADC08351 input isolates the amplifi-
er’s output from the current transients at the input to the
converter.
When the signal source is not located close to the converter,
the signal should be buffered. Figure 6 shows an example of
an appropriate buffer. The amplifier provides a gain of two to
compensate for transmission losses.
Operational amplifiers have better linearity when they oper-
ate with gain, so the input is attenuated with the 68
Ω and
30 Ω resistors at the non-inverting input. The 330Ω resistor in
parallel with these two resistors provides for a 75
Ω cable
termination. Replacing this 330 Ω resistor with one of 100Ω
will provide a 50 Ω termination.
The circuit shown has a nominal gain of two. You can provide
a gain adjustment by changing the 110
Ω feedback resistor to
a 100 Ω resistor in series with a 20Ω potentiometer.
The offset adjustment is used to bring the input signal within
the common mode range of the converter. If a fixed offset is
desired, the potentiometer and the 3.3k resistor may be
replaced with a single resistor of 3k to 4k to the appropriate
supply. The resistor value and the supply polarity used will
depend upon the amount and polarity of offset needed.
The CLC409 shown in Figure 6 was chosen for a low cost
solution with good overall performance.
Figure 7 shows an inverting DC coupled circuit. The above
comments regarding Figure 6 generally apply to this circuit
as well.
10089526
FIGURE 4. Isolating the ADC Clock from Digital
Circuitry
ADC08351
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