Rainbow Electronics ADC08351 - Manual (Page 9)

Timing Diagram
Functional Description
The ADC08351 achieves 6.8 effective bits at 21 MHz input
frequency with 42 MHz clock frequency digitizing to eight bits
the analog signal at V
IN
that is within the nominal voltage
range of 0.5 V
P-P
to 0.68 V
A
.
Input voltages below 0.0665 times the reference voltage will
cause the output word to consist of all zeroes, while input
voltages above
3 ⁄
4
of the reference voltage will cause the
output word to consist of all ones. For example, with a V
REF
of 2.4V, input voltages below 160 mV will result in an output
word of all zeroes, while input voltages above 1.79V will
result in an output word of all ones.
The output word rate is the same as the clock frequency.
Data is acquired at the falling edge of the clock and the
digital equivalent of that data is available at the digital out-
puts 2.5 clock cycles plus t
OD
later. The ADC08351 will
convert as long as the clock signal is present at the CLK pin,
but the data will not appear at the outputs unless the OE pin
is low. The digital outputs are in the high impedance state
when the OE pin or when the PD pin is high.
Applications Information
(All schematic
pin numbers refer to the TSSOP.)
1.0 THE ADC REFERENCE AND THE ANALOG INPUT
The capacitance seen at the input changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than is a fixed capacitance, choose an
amplifier that can drive this type of load. The CLC409,
10089523
FIGURE 1. ADC08351 Timing Diagram
10089524
FIGURE 2. t
EN
, t
DIS
Test Circuit
ADC08351
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