Rainbow Electronics ADC08351 - Manual (Page 15)

Applications Information
(All schematic
pin numbers refer to the TSSOP.) (Continued)
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV beyond the supply rails. That is, more
than 300 mV below the ground pins or 300 mV above the
supply pins. Exceeding these limits on even a transient basis
may cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground
or above the power supply. Since these conditions are of
very short duration with very fast rise and fall times, they can
inject noise into the system and may be difficult to detect with
an oscilloscope. A resistor of about 50
Ω to 100Ω in series
with the offending digital input will usually eliminate the
problem.
Care should be taken not to overdrive the inputs of the
ADC08351 (or any device) with a device that is powered
from supplies outside the range of the ADC08351 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from V
D
and DGND. These large charging current
spikes can couple into the analog section, degrading dy-
namic performance. While adequate bypassing and main-
taining separate analog and digital ground planes will reduce
this problem on the board, this coupling can still occur on the
ADC08351 die. Buffering the digital data outputs (with a
74ACQ541, for example) may be necessary if the data bus
to be driven is heavily loaded.
Dynamic performance can also be improved by adding se-
ries resistors at each digital output, reducing the energy
coupled back into the converter output pins by limiting the
output slew rate. A reasonable value for these resistors is
about 47
Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the
input alternates between 4 pF and 11 pF with the clock. This
dynamic capacitance is more difficult to drive than a fixed
capacitance, so care should be taken in choosing a driving
device. The CLC409, CLC440, LM6152, LM6154, LM6181
and LM6182 are good devices for driving the ADC08351.
Also, an amplifier with insufficient gain-bandwidth may limit
the overall frequency response of the overall circuit.
Using an operational amplifier in an insufficient gain
configuration to drive the analog input. Operational am-
plifiers, while some may be unity gain stable, generally ex-
hibit more distortion at low in-circuit gains than at higher
gains.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate.
Not considering the timing relationships, especially t
OD
.
Timing is always important and gets more critical with higher
speeds. If the output data is latched or looked at when that
data is in transition, you may see excessive noise and
distortion of the output signal.
ADC08351
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