Rainbow Electronics ATmega64L - Manual (Page 45)

45
ATmega16(L)
2466B–09/01
Moving Interrupts Between
Application and Boot Space The General Interrupt Control Register controls the placement of the interrupt vector
table.
General Interrupt Control
Register – GICR
• Bit 1 - IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the
Flash memory. When this bit is set (one), the interrupt vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address of the start of the boot
Flash section is determined by the BOOTSZ fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-Programming” on page 240 for details. To avoid unin-
tentional changes of interrupt vector tables, a special write procedure must be followed
to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02
is programmed, interrupts are disabled while executing from the Application section. If
interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is pro-
gramed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-Programming” on page 240
for details on Boot Lock bits.
• Bit 0 - IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code
Example below.
Bit 7 6 5 4 3 2 1 0
INT1 INT0 INT2 – – – IVSEL IVCE GICR
Read/Write R/W R/W R/W R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0