1 chapter overview, 2 microstrip or stripline, 3 pcb stackup example – IEI Integration ICE-DB-T6 User Manual

Page 77: Hapter, Verview, Icrostrip or, Tripline, Tackup, Xample

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Type 6 Carrier Board Design Guide

Page 67

4.1 Chapter Overview

A brief description of the Printed Circuit Board (PCB) for COM Express based board is

provided in this section. From a cost- effectiveness point of view, a four-layer board is the

target platform for the motherboard design. For better quality, a six-layer or 8-layer board

is preferred. This chapter also provides the ATX/AT power supply design recommendation

for customer’s reference. IEI ICE module carrier board use 4-layer PCB stack.

4.2 Microstrip or Stripline

Either edge-coupled microstrip, edge-coupled stripline, or broad-side striplines are

recommended for designs with differential signals. Microstrip lines have the advantage

that a lower number of layers can be used. With microstrip lines, it may be possible to

route from a connector pad to the device pad without any via. This provides better signal

quality on the signal path that connects devices. Microstrip lines can only be routed on the

two outside layers of the PCB, thus routing channel density is limited.

Stripline may be either edge-coupled or broad-side coupled lines. Stripline designs

provide additional shielding since they are embedded in the board stack and are typically

in between ground and power planes. This reduces radiation and coupling of noise onto

the lines. Striplines offer the disadvantage that they require the use of vias to connect to

them.

4.3 PCB Stackup Example

It is recommended to use PCB's with at least a 4-layer stackup where the impedance

controlled top layer (layer 1) is used for differential signals and bottom layer (layer 4) for

other periodic signals (CMOS/TTL). The dedicated power planes (layer 2 – GND and layer

3 – VCC) are required for high-speed designs. It is necessary for the solid ground plane to

establish a controlled impedance for the transmission line interconnects. A narrow spacing

between ground and power planes will create an excellent high frequency bypass

capacitance additionally. The following example shows a four layer PCB stackup using

microstrip trace routing. A good rule to follow for microstrip designs is to keep S < W and S

< H (“H” = space between differential signal layers and the reference plane). The best

practice is to use the closest spacing, “S,” allowed by the PCB vendor and then adjust

trace widths, “W,” to control differential impedance.

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