ARM VERSION 1.2 - Manual (Page 200)

Thumb Instruction Reference
5-6 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
Address alignment for word and halfword transfers
The address must be divisible by 4 for word transfers, and by 2 for halfword transfers.
If your system has a system coprocessor (cp15), you can enable alignment checking.
Non-aligned transfers cause an alignment exception if alignment checking is enabled.
If your system does not have a system coprocessor (cp15), or alignment checking is
disabled:
• A non-aligned load corrupts Rd .
• A non-aligned save corrupts two or four bytes in memory. The corrupted location
in memory is [address AND NOT
0x1 ] for halfword saves, and [address AND
NOT 0x3 ] for word saves.
Architectures
These instructions are available in all T variants of the ARM architecture.
Examples
LDR r3,[r5,#0]
STRB r0,[r3,#31]
STRH r7,[r3,#16]
LDRB r2,[r4,#label-{PC}]
Incorrect examples
LDR r13,[r5,#40] ; high registers not allowed
STRB r0,[r3,#32] ; 32 is out of range for byte transfers
STRH r7,[r3,#15] ; offsets for halfword transfers must be even
LDRH r6,[r0,#-6] ; negative offsets not supported