Cirrus Logic CS2300-OTP - Manual (Page 15)

CS2300-OTP
DS844F2 15
5.5 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
Figure 11. PLL Clock Output Options
Referenced Control Parameter Definition
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 20
ClkOutDis .............................. “M2 Configured as Output Disable” on page 17
M2Config[2:0]........................ “M2 Pin Configuration (M2Config[2:0])” on page 21
PLL Locked/Unlocked
PLL Output
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut