Cirrus Logic CS2300-OTP - Manual (Page 21)

CS2300-OTP
DS844F2 21
6.3.4 M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin .
6.3.5 Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
M2Config[2:0] M2 pin function
000 Disable CLK_OUT pin.
001 Disable AUX_OUT pin.
010 Disable CLK_OUT and AUX_OUT.
011 RModSel[1:0] Modal Parameter Enable.
100 Reserved.
101 Reserved.
110 Reserved.
111 Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
Application: “M2 Mode Pin Functionality” on page 17
ClkIn_BW[2:0] Minimum Loop Bandwidth
000 1 Hz
001 2 Hz
010 4 Hz
011 8 Hz
100 16 Hz
101 32 Hz
110 64 Hz
111 128 Hz
Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 11