Cirrus Logic CRD5376 - Manual (Page 25)

CRD5376
DS612RD2 25
2.3.2.5 Timebreak Signal
By default, the C8051F320 microcontroller sends the TIMEB signal to the digital filter for the first collected
sample of a data record. By default, 100 initial samples are skipped during data collection to ensure the
CS5376A digital filters are fully settled, and the timebreak signal is automatically set for the first ‘real’ col-
lected sample.
2.3.2.6 C2 Debug Interface
Through the PC evaluation software, the microcontroller default firmware can be automatically flashed to
the latest version without connecting an external programmer. To flash custom firmware, software tools
and an inexpensive hardware programmer that connects to the C2 Debug Interface on CRD5376 is avail-
able for purchase from Silicon Laboratories (DEBUGADPTR1-USB).
2.3.3 Phase Locked Loop
To make synchronous analog measurements throughout a distributed system, a synchronous system
clock is required to be provided to each measurement node. CRD5376 can receive a lower frequency sys-
tem clock through the external connector and create a synchronous higher frequency clock using an on-
board PLL.
The expected input clock frequency to the external connector is set by jumper options. If no external clock
is supplied to CRD5376, the PLL will free-run at the nominal output frequency. A jumper option is available
to output the clock to the external connector, making it the system clock source.
Specification Value
Input Clock Frequency
1.024, 2.048, 4.096 MHz
Distributed Clock Synchronization ± 240 ns
Maximum Input Clock Jitter, RMS 1 ns
Specification Value
PLL Output Clock Frequency
32.768 MHz
Maximum Output Jitter, RMS 300 ps
Oscillator Type VCXO
Detector Architecture Phase / Frequency
Input Clock Jumper
1.024 MHz R16
2.048 MHz R18
4.096 MHz R82
Table 8. Clock Input / Output Jumper Settings
Output Clock Jumpers
1.024 MHz R68 + R16
2.048 MHz R68 + R18
4.096 MHz R68 + R82