Cirrus Logic CS42418 - Manual (Page 13)

DS603F2 13
CS42418
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
™
FORMAT
(T
A
= -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC,
C
L
= 30 pF)
Notes:
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f
sck
<1 MHz.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency f
sck
0 - 6.0 MHz
CS High Time Between Transmissions t
csh
1.0 - - s
CS Falling to CCLK Edge t
css
20 - - ns
CCLK Low Time t
scl
66 - - ns
CCLK High Time t
sch
66 - - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - - ns
CCLK Rising to DATA Hold Time (Note 20) t
dh
15 - - ns
CCLK Falling to CDOUT Stable t
pd
- - 50 ns
Rise Time of CDOUT t
r1
- - 25 ns
Fall Time of CDOUT t
f1
- - 25 ns
Rise Time of CCLK and CDIN (Note 21) t
r2
- - 100 ns
Fall Time of CCLK and CDIN (Note 21) t
f2
- - 100 ns
t r2 t f2
t dsu
t dh
t sch t scl
CS
CCLK
CDIN
t css
t pd
CDOUT
t csh
Figure 4. Control Port Timing - SPI Format