Cirrus Logic CS42418 - Manual (Page 31)

DS603F2 31
CS42418
4.5.4 One-Line Mode (OLM) Configurations
4.5.4.1 OLM Config #1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, and 6 channels of ADC data.
This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on
all channels for both the DAC and ADC.
Register / Bit Settings Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = ADC_FMx = 00,01,10 DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported
Set ADC_CLK_SEL = 0 Configure ADC_SDOUT to be clocked from the DAC_SP clocks.
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format Select the digital interface format when not in One-Line Mode
Set ADC_OLx bits = 00,01,10 Select ADC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01,10 Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1 Configure DAC Serial Port to Master Mode.
Set ADC_SP M/S = 1 Configure ADC Serial Port to Master Mode.
Set EXT ADC SCLK = 0 Identify external ADC clock source as SAI Serial Port.
DAC Mode
Not One-Line Mode One-Line Mode #1 One-Line Mode #2
ADC Mode
Not One-
Line Mode
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
One-Line
Mode #1
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
One-Line
Mode #2
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
SCLK_PORT1
LRCK_PORT1
SDIN_PORT1
SCLK_PORT2
LRCK_PORT2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
SDOUT4_PORT2
ADC_SCLK
ADC_LRCK
DAC_SCLK
DAC_LRCK
ADC_SDOUT
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
RMCK
ADCIN1
ADCIN2
MCLK
SDOUT1
SDOUT2
LRCK
SCLK
64Fs
ADC Data
64Fs,128Fs, 256Fs
DIGITAL AUDIO
PROCESSOR
CS5361
CS5361
MCLK
Figure 17. OLM Configuration #1
CS42418