2 master clock 2 frequency (bits 2:0), Table 13. mclk 2 frequency, 6 signal selection - address 06h – Cirrus Logic CS4245 User Manual

Page 46: 1 auxiliary output source select (bits 6:5), Table 14. auxiliary output source selection, 2 digital loopback (bit 1), 3 asynchronous mode (bit 0), Section 6.6.1, Cs4245

Advertising
2 master clock 2 frequency (bits 2:0), Table 13. mclk 2 frequency, 6 signal selection - address 06h | 1 auxiliary output source select (bits 6:5), Table 14. auxiliary output source selection, 2 digital loopback (bit 1), 3 asynchronous mode (bit 0), Section 6.6.1, Cs4245 | Cirrus Logic CS4245 User Manual | Page 46 / 59 2 master clock 2 frequency (bits 2:0), Table 13. mclk 2 frequency, 6 signal selection - address 06h | 1 auxiliary output source select (bits 6:5), Table 14. auxiliary output source selection, 2 digital loopback (bit 1), 3 asynchronous mode (bit 0), Section 6.6.1, Cs4245 | Cirrus Logic CS4245 User Manual | Page 46 / 59
Advertising
See also other documents in the category Cirrus Logic Hardware: