Cirrus Logic CS4245 - Manual (Page 4)

4 DS656F3
CS4245
6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 43
6.2.5 Power-Down Device (Bit 0) ................................................................................................... 43
6.3 DAC Control - Address 03h ............................................................................................................ 43
6.3.1 DAC Functional Mode (Bits 7:6) ............................................................................................ 43
6.3.2 DAC Digital Interface Format (Bits 5:4) ................................................................................. 43
6.3.3 Mute DAC (Bit 2) ................................................................................................................... 43
6.3.4 De-Emphasis Control (Bit 1) .................................................................................................. 44
6.3.5 DAC Master / Slave Mode (Bit 0) .......................................................................................... 44
6.4 ADC Control - Address 04h ............................................................................................................ 44
6.4.1 ADC Functional Mode (Bits 7:6) ............................................................................................ 44
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 45
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 45
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 45
6.4.5 ADC Master / Slave Mode (Bit 0) .......................................................................................... 45
6.5 MCLK Frequency - Address 05h .................................................................................................... 45
6.5.1 Master Clock 1 Frequency (Bits 6:4) ..................................................................................... 45
6.5.2 Master Clock 2 Frequency (Bits 2:0) ..................................................................................... 46
6.6 Signal Selection - Address 06h ...................................................................................................... 46
6.6.1 Auxiliary Output Source Select (Bits 6:5) .............................................................................. 46
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 46
6.6.3 Asynchronous Mode (Bit 0) ................................................................................................... 46
6.7 Channel B PGA Control - Address 07h .......................................................................................... 47
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 47
6.8 Channel A PGA Control - Address 08h .......................................................................................... 47
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 47
6.9 ADC Input Control - Address 09h ................................................................................................... 47
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 47
6.9.2 Analog Input Selection (Bits 2:0) ........................................................................................... 48
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 48
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 48
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 48
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 49
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 49
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 49
6.12.3 Active High/Low (Bit 0) ........................................................................................................ 50
6.13 Interrupt Status - Address 0Dh ..................................................................................................... 50
6.13.1 ADC Clock Error (Bit 3) ....................................................................................................... 50
6.13.2 DAC Clock Error (Bit 2) ....................................................................................................... 50
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 50
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 50
6.14 Interrupt Mask - Address 0Eh ....................................................................................................... 50
6.15 Interrupt Mode MSB - Address 0Fh .............................................................................................. 51
6.16 Interrupt Mode LSB - Address 10h ............................................................................................... 51
7. PARAMETER DEFINITIONS ................................................................................................................ 52
8. DAC FILTER PLOTS .................................................................................................................... 53
9. ADC FILTER PLOTS ......................................................................................................................... 55
10. PACKAGE DIMENSIONS .................................................................................................................. 57
11. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 57
12. ORDERING INFORMATION ..................................................................................................... 58
13. REVISION HISTORY .......................................................................................................................... 58