Cirrus Logic CS4245 - Manual (Page 37)

DS656F3 37
CS4245
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
The MUTEC pin is an active-low CMOS driver. See Figure 16 for a suggested active-low mute circuit.
4.12 Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS4245 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.12.1 SPI Mode
In SPI Mode, CS is the CS4245 chip-select signal; CCLK is the control port bit clock (input into the CS4245
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 k resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
LPF
+V
EE
-V
EE
560 
Audio
Out
2 k
10 k
-V
EE
+V
A
MMUN2111LT1
AOUT
MUTEC
AC
Couple
47 k
Figure 16. Suggested Active-Low Mute Circuit
CS4245