Cirrus Logic CS4245 - Manual (Page 5)

DS656F3 5
CS4245
LIST OF FIGURES
Figure 1.DAC Output Test Load ................................................................................................................ 12
Figure 2.Maximum DAC Loading .............................................................................................................. 12
Figure 3.Master Mode Timing - Serial Audio Port 1 .................................................................................. 23
Figure 4.Slave Mode Timing - Serial Audio Port 1 .................................................................................... 23
Figure 5.Master Mode Timing - Serial Audio Port 2 .................................................................................. 25
Figure 6.Slave Mode Timing - Serial Audio Port 2 .................................................................................... 25
Figure 7.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 26
Figure 8.Format 1, I²S up to 24-Bit Data ................................................................................................... 26
Figure 9.Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 26
Figure 10.Control Port Timing - I²C Format ............................................................................................... 27
Figure 11.Control Port Timing - SPI Format .............................................................................................. 28
Figure 12.Typical Connection Diagram ..................................................................................................... 29
Figure 13.Master Mode Clocking .............................................................................................................. 32
Figure 14.Analog Input Architecture .......................................................................................................... 34
Figure 15.De-Emphasis Curve .................................................................................................................. 36
Figure 16.Suggested Active-Low Mute Circuit .......................................................................................... 37
Figure 17.Control Port Timing in SPI Mode .............................................................................................. 38
Figure 18.Control Port Timing, I²C Write ................................................................................................... 38
Figure 19.Control Port Timing, I²C Read ................................................................................................... 39
Figure 20.De-Emphasis Curve .................................................................................................................. 44
Figure 21.DAC Single-Speed Stopband Rejection ................................................................................... 53
Figure 22.DAC Single-Speed Transition Band .......................................................................................... 53
Figure 23.DAC Single-Speed Transition Band .......................................................................................... 53
Figure 24.DAC Single-Speed Passband Ripple ........................................................................................ 53
Figure 25.DAC Double-Speed Stopband Rejection .................................................................................. 53
Figure 26.DAC Double-Speed Transition Band ........................................................................................ 53
Figure 27.DAC Double-Speed Transition Band ........................................................................................ 54
Figure 28.DAC Double-Speed Passband Ripple ...................................................................................... 54
Figure 29.DAC Quad-Speed Stopband Rejection ..................................................................................... 54
Figure 30.DAC Quad-Speed Transition Band ........................................................................................... 54
Figure 31.DAC Quad-Speed Transition Band ........................................................................................... 54
Figure 32.DAC Quad-Speed Passband Ripple ......................................................................................... 54
Figure 33.ADC Single-Speed Stopband Rejection ................................................................................... 55
Figure 34.ADC Single-Speed Stopband Rejection ................................................................................... 55
Figure 35.ADC Single-Speed Transition Band (Detail) ............................................................................. 55
Figure 36.ADC Single-Speed Passband Ripple ........................................................................................ 55
Figure 37.ADC Double-Speed Stopband Rejection .................................................................................. 55
Figure 38.ADC Double-Speed Stopband Rejection .................................................................................. 55
Figure 39.ADC Double-Speed Transition Band (Detail) ............................................................................ 56
Figure 40.ADC Double-Speed Passband Ripple ...................................................................................... 56
Figure 41.ADC Quad-Speed Stopband Rejection ..................................................................................... 56
Figure 42.ADC Quad-Speed Stopband Rejection ..................................................................................... 56
Figure 43.ADC Quad-Speed Transition Band (Detail) .............................................................................. 56
Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 56
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 30
Table 2. Common Clock Frequencies ....................................................................................................... 31
Table 3. Slave Mode MCLK Dividers ........................................................................................................ 31
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 32
Table 5. Device Revision .......................................................................................................................... 42