Cirrus Logic CRD42L52 - Manual (Page 5)

DS680RD1 5
CRD42L52
1.5 Oscillator (Y1)
The on-board oscillator provides the system master clock when the digital audio receiver is powered down
or when a receiver error occurs in the CS8416. Internal circuitry in the CS8416 automatically sets the oscil-
lator clock as the new system clock whenever a receiver error is detected. This feature allows users to op-
erate the boards without having a S/PDIF input fed to the board at all times.
1.6 CS42L52 Audio CODEC (U1)
A complete description of the CS42L52 ( Figure 21 on page 20 ) is included in the CS42L52 product data
sheet. The CS42L52 is configured using the Windows-compatible Cirrus FlexGUI software provided. The
I²C control port interface on the CS42L52 can be used for register manipulation and is controlled by the
microcontroller on the CDB42LDB1 driver board.
For full details on software functionality, refer to Section 4. "Software Mode Control" .
1.7 Analog Input
A 1/8” stereo jack can be used to supply stereo line-level analog inputs to the CS42L52 up to a full-scale
value of 2 Vrms. An AC-coupled passive filter and a voltage divider scale down the signal before sending it
to the CS42L52 to prevent the signal from clipping.
The CRD42L52 is routed to only allow analog inputs on input channel 1 of the CS42L52. Analog Input Chan-
nels 2, 3 and 4 and Microphone Input Channels 1 and 2 are not connected.
1.8 Analog Outputs
The analog output from the CS42L52’s ground-centered headphone amplifier can be monitored on the 1/8”
stereo jack on the CRD42L52. Alternatively, one can also monitor the differential stereo PWM speaker out-
put on the CS42L52 by using the differential speaker terminals J3 and J4.
1.9 Layout
The CS42L52 requires only a minimal set of components to achieve specified performance results. Its inte-
grated ground-centered amplifier eliminates the need for bulky DC-blocking capacitors and only requires
two tiny ceramic capacitors for the charge pump. Additional components include load-stabilization circuitry
and power supply decoupling. See the CS42L52 data sheet for further details.
Figure 20 on page 19 provides an overview of the connections to the CS42L52. Figure 24 on page 23 and
Figure 25 on page 23 show the component placement. Figure 26 on page 23 shows the top layout; Figure
27 on page 23 and Figure 28 on page 23 show the inner layers, and Figure 29 on page 23 shows the bottom
layout. The decoupling capacitors are located as close to the CS42L52 as possible. Extensive use of ground
plane fill in the reference design yields large reductions in radiated noise.