Cirrus Logic CRD42L52 - Manual (Page 7)

DS680RD1 7
CRD42L52
3. CONFIGURATION OPTIONS
This section provides a deeper understanding of on-board circuitry and digital clock and data signal routing for ap-
propriately setting the control software in a specific configuration. The section also provides the expected perfor-
mance characteristics for the respective configuration mode.
Figure 2. CRD42L52 and CDB42LDB1 Block Diagram for ADC and DAC Testing
In order to test the ADC, DAC and PWM on the CS42L52, S/PDIF digital input needs to be provided to the CS8416
S/PDIF receiver on the CDB42LDB1 driver board via optical or RCA input jacks. The CS8416 operates in master
mode and drives the serial audio interface lines to the CS42L52 and the CS8406, as shown in
Figure 2 . For correct
CS42L52 serial port operation, the CS42L52 serial port should be set up as a slave and the “Driver Board Serial
Port” needs to be enabled in the FlexGUI software.
3.1 S/PDIF In to Headphone Out
Stereo headphone-level analog outputs can be monitored on stereo jack J8 on the CRD42L52. Serial Audio
digital clocks and data is routed to the CRD42L52 via I/O header J3.
Table 1 shows expected performance
characteristics when the boards are configured to make digital input to analog output measurements.
3.2 Line In to S/PDIF Out
Line-level analog input can be provided to the CS42L52 via stereo jack J7 on the CRD42L52. The analog
input path on the CRD42L52 scales the input down to a fifth of its actual value. Therefore, a 2.4 Vrms analog
input into the CRD42L52 is required to provide full-scale input to the CS42L52. The ADC core uses the
clocks provided to the CS42L52 by the CS8416 to perform the conversion and outputs data to the CS8406
S/PDIF transmitter on the CDB42LDB1 driver board via the I/O header, J3. The S/PDIF output can be mon-
itored on the RCA or optical jacks (J9 and J7).
Plot Location
FFT - S/PDIF In to Headphone Out @ 0 dBFS Figure 12 on page 15
FFT - S/PDIF In to Headphone Out @ -60 dB FS Figure 13 on page 16
Dynamic Range - S/PDIF In to Headphone Out Figure 14 on page 16
Frequency Response - S/PDIF In to Headphone Out Figure 15 on page 16
THD + N - S/PDIF In to Headphone Out Figure 16 on page 16
Table 1. S/PDIF In to Headphone Out Performance Plots
CS42L52
CS8416
S/PDIF Rx
RMCK
LRCLK
SCLK
SDOUT
CS8406
S/PDIF Tx
S/PDIF
IN
S/PDIF
OUT
AIN1A
AIN1B
R
T
Line
Input
(MASTER)
(SLAVE)
(SLAVE)
MCLK
LRCLK
SCLK
SDIN
12.288 MHz
Oscillator
T
R
Headphone
Output
HP/ LINE_OUTA
HP/ LINE_OUTB
SPKR_OUTB+
SPKR_OUTB-
SPKR_OUTA-
SPKR_OUTA+
CRD42L52
OMCK
Left
Right
Serial
Port
Enable